diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala
index 7b73511d..445dea95 100644
--- a/uncore/src/main/scala/tilelink.scala
+++ b/uncore/src/main/scala/tilelink.scala
@@ -1295,11 +1295,6 @@ trait HasDataBeatCounters {
   }
 }
 
-class ClientTileLinkIOUnwrapperInfo extends Bundle {
-  val voluntary = Bool()
-  val builtin = Bool()
-}
-
 class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
   val io = new Bundle {
     val in = new ClientTileLinkIO().flip
diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala
index 80310966..a86a7525 100644
--- a/uncore/src/main/scala/util.scala
+++ b/uncore/src/main/scala/util.scala
@@ -131,7 +131,8 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Int)
   val roq_free = Reg(init = Vec.fill(size)(Bool(true)))
 
   val roq_enq_addr = PriorityEncoder(roq_free)
-  val roq_matches = roq_tags.map(_ === io.deq.tag)
+  val roq_matches = roq_tags.zip(roq_free)
+    .map { case (tag, free) => tag === io.deq.tag && !free }
   val roq_deq_addr = PriorityEncoder(roq_matches)
 
   io.enq.ready := roq_free.reduce(_ || _)