riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor

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This commit is contained in:
Richard Xia
2016-09-16 17:10:52 -07:00
parent 851a336db4 4abba87b61
commit 63f13ae7ce
33 changed files with 632 additions and 337 deletions
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7
src/main/scala/rocketchip/TestHarness.scala
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@ -12,11 +12,12 @@ import junctions.NastiConstants._
case object BuildExampleTop extends Field[Parameters => ExampleTop]
case object SimMemLatency extends Field[Int]
class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapParameters {
class TestHarness(q: Parameters) extends Module {
val io = new Bundle {
val success = Bool(OUTPUT)
}
val dut = p(BuildExampleTop)(p).module
val dut = q(BuildExampleTop)(q).module
implicit val p = dut.p
// This test harness isn't especially flexible yet
require(dut.io.mem_clk.isEmpty)
@ -34,7 +35,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapPara
int := false
if (dut.io.mem_axi.nonEmpty) {
val memSize = addrMap("mem").size
val memSize = p(GlobalAddrMap)("mem").size
require(memSize % dut.io.mem_axi.size == 0)
for (axi <- dut.io.mem_axi) {
val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi.size))