Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor
This commit is contained in:
Richard Xia
@ -20,9 +20,6 @@ import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BasePlatformConfig extends Config(
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topDefinitions = {
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val configString = new GlobalVariable[String]
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val globalAddrMap = new GlobalVariable[AddrMap]
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val nCoreplexExtClients = new GlobalVariable[Int]
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(pname,site,here) => {
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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@ -55,7 +52,6 @@ class BasePlatformConfig extends Config(
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case NExtMMIOTLChannels => 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NCoreplexExtClients => nCoreplexExtClients
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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@ -69,8 +65,6 @@ class BasePlatformConfig extends Config(
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => configString
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case GlobalAddrMap => globalAddrMap
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTop(p))
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@ -152,6 +146,7 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
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class WithMIFDataBits(n: Int) extends Config(
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(pname, site, here) => pname match {
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case MIFDataBits => Dump("MIF_DATA_BITS", n)
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case _ => throw new CDEMatchError
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})
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class MIF128BitConfig extends Config(
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@ -182,12 +177,14 @@ class TinyConfig extends Config(
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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case AsyncDebugBus => true
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case AsyncDebugBus => true
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case _ => throw new CDEMatchError
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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case IncludeJtagDTM => true
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case IncludeJtagDTM => true
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case _ => throw new CDEMatchError
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}
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)
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@ -56,6 +56,10 @@ trait HasGeneratorUtilities {
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}
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}
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object ConfigStringOutput {
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var contents: Option[String] = None
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}
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trait Generator extends App with HasGeneratorUtilities {
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lazy val names = {
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require(args.size == 5, "Usage: sbt> " +
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@ -67,20 +71,25 @@ trait Generator extends App with HasGeneratorUtilities {
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configProject = args(3),
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configs = args(4))
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}
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lazy val td = names.targetDir
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lazy val config = getConfig(names)
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lazy val world = config.toInstance
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lazy val params = Parameters.root(world)
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lazy val circuit = elaborate(names, params)
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lazy val longName = names.topModuleClass + "." + names.configs
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def writeOutputFiles() {
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TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
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writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
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writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
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writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
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writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
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ConfigStringOutput.contents.foreach(c => writeOutputFile(td, s"${names.configs}.cfg", c)) // String for software
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}
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}
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object RocketChipGenerator extends Generator {
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val longName = names.topModuleClass + "." + names.configs
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val td = names.targetDir
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Driver.dumpFirrtl(circuit, Some(new File(td, s"$longName.fir"))) // FIRRTL
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TestGeneration.addSuite(new RegressionTestSuite(params(RegressionTestNames)))
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writeOutputFile(td, s"$longName.d", TestGeneration.generateMakefrag) // Coreplex-specific test suites
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writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
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writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
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writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
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writeOutputFile(td, s"${names.configs}.cfg", params(ConfigString).get) // String for software
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writeOutputFiles()
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}
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@ -7,11 +7,13 @@ import cde.{Parameters, Field}
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import junctions._
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import junctions.NastiConstants._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule, LazyModuleImp}
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import uncore.tilelink2._
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import uncore.converters._
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import uncore.devices._
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import uncore.util._
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import rocket.Util._
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import rocket.XLen
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import scala.math.max
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import coreplex._
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/** Options for memory bus interface */
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@ -202,10 +204,10 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryMasterMMIO
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val io: PeripheryMasterMMIOBundle
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val mmioNetwork: Option[TileLinkRecursiveInterconnect]
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val mmioNetwork: TileLinkRecursiveInterconnect
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val mmio_ports = p(ExtMMIOPorts) map { port =>
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TileLinkWidthAdapter(mmioNetwork.get.port(port.name), "MMIO_Outermost")
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TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost")
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}
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val mmio_axi_start = 0
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@ -277,37 +279,47 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
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/////
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/** Always-ON block */
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trait PeripheryAON extends LazyModule {
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trait PeripheryCoreplexLocalInterrupter extends LazyModule with HasPeripheryParameters {
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implicit val p: Parameters
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val peripheryBus: TLXbar
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// CoreplexLocalInterrupter must be at least 64b if XLen >= 64
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val beatBytes = (innerMMIOParams(XLen) min 64) / 8
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val clintConfig = CoreplexLocalInterrupterConfig(beatBytes)
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val clint = LazyModule(new CoreplexLocalInterrupter(clintConfig)(innerMMIOParams))
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// The periphery bus is 32-bit, so we may need to adapt its width to XLen
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clint.node := TLFragmenter(TLWidthWidget(peripheryBus.node, 4), beatBytes, 256)
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// TL1 legacy
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val pDevices: ResourceManager[AddrMapEntry]
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pDevices.add(AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW))))
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pDevices.add(AddrMapEntry("clint", MemRange(clintConfig.address, clintConfig.size, MemAttr(AddrMapProt.RW))))
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}
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trait PeripheryAONBundle {
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trait PeripheryCoreplexLocalInterrupterBundle {
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implicit val p: Parameters
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}
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trait PeripheryAONModule extends HasPeripheryParameters {
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trait PeripheryCoreplexLocalInterrupterModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryAON
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val io: PeripheryAONBundle
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val mmioNetwork: Option[TileLinkRecursiveInterconnect]
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val outer: PeripheryCoreplexLocalInterrupter
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val io: PeripheryCoreplexLocalInterrupterBundle
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val coreplex: Coreplex
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val prci = Module(new PRCI()(innerMMIOParams))
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prci.io.rtcTick := Counter(p(RTCPeriod)).inc()
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prci.io.tl <> mmioNetwork.get.port("prci")
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coreplex.io.prci <> prci.io.tiles
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outer.clint.module.io.rtcTick := Counter(p(RTCPeriod)).inc()
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coreplex.io.clint <> outer.clint.module.io.tiles
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}
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/////
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trait PeripheryBootROM extends LazyModule {
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implicit val p: Parameters
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val pDevices: ResourceManager[AddrMapEntry]
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val peripheryBus: TLXbar
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val rom = LazyModule(new TLROM(0x1000, 0x1000, GenerateBootROM(p)))
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rom.node := TLFragmenter(peripheryBus.node, 4, 256)
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// TL1 legacy address map
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val pDevices: ResourceManager[AddrMapEntry]
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pDevices.add(AddrMapEntry("bootrom", MemRange(0x1000, 4096, MemAttr(AddrMapProt.RX))))
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}
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@ -319,20 +331,23 @@ trait PeripheryBootROMModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryBootROM
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val io: PeripheryBootROMBundle
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val mmioNetwork: Option[TileLinkRecursiveInterconnect]
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val bootROM = Module(new ROMSlave(GenerateBootROM(p))(innerMMIOParams))
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bootROM.io <> mmioNetwork.get.port("bootrom")
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}
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/////
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trait PeripheryTestRAM extends LazyModule {
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implicit val p: Parameters
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val pDevices: ResourceManager[AddrMapEntry]
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val peripheryBus: TLXbar
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val ramBase = 0x52000000
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val ramSize = 0x1000
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pDevices.add(AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))))
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val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)))
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sram.node := TLFragmenter(peripheryBus.node, 4, 256)
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// TL1 legacy address map
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val pDevices: ResourceManager[AddrMapEntry]
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pDevices.add(AddrMapEntry("testram", MemRange(ramBase, ramSize, MemAttr(AddrMapProt.RW))))
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}
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trait PeripheryTestRAMBundle {
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@ -342,22 +357,16 @@ trait PeripheryTestRAMBundle {
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trait PeripheryTestRAMModule extends HasPeripheryParameters {
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implicit val p: Parameters
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val outer: PeripheryTestRAM
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val io: PeripheryTestRAMBundle
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val mmioNetwork: Option[TileLinkRecursiveInterconnect]
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val testram = Module(new TileLinkTestRAM(outer.ramSize)(innerMMIOParams))
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testram.io <> mmioNetwork.get.port("testram")
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}
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/////
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trait PeripheryTestBusMaster extends LazyModule {
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implicit val p: Parameters
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val pBusMasters: RangeManager
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val pDevices: ResourceManager[AddrMapEntry]
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val peripheryBus: TLXbar
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pBusMasters.add("busmaster", 1)
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pDevices.add(AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW))))
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val fuzzer = LazyModule(new TLFuzzer(5000))
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peripheryBus.node := fuzzer.node
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}
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trait PeripheryTestBusMasterBundle {
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@ -367,16 +376,4 @@ trait PeripheryTestBusMasterBundle {
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trait PeripheryTestBusMasterModule {
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implicit val p: Parameters
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val outer: PeripheryTestBusMaster
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val io: PeripheryTestBusMasterBundle
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val mmioNetwork: Option[TileLinkRecursiveInterconnect]
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val coreplex: Coreplex
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val busmaster = Module(new groundtest.ExampleBusMaster()(p))
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busmaster.io.mmio <> mmioNetwork.get.port("busmaster")
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{
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val r = outer.pBusMasters.range("busmaster")
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require(r._2 - r._1 == 1, "RangeManager should return 1 slot")
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coreplex.io.slave(r._1) <> busmaster.io.mem
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}
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}
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@ -12,11 +12,12 @@ import junctions.NastiConstants._
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case object BuildExampleTop extends Field[Parameters => ExampleTop]
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case object SimMemLatency extends Field[Int]
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class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapParameters {
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class TestHarness(q: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val dut = p(BuildExampleTop)(p).module
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val dut = q(BuildExampleTop)(q).module
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implicit val p = dut.p
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// This test harness isn't especially flexible yet
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require(dut.io.mem_clk.isEmpty)
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@ -34,7 +35,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapPara
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int := false
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if (dut.io.mem_axi.nonEmpty) {
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val memSize = addrMap("mem").size
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val memSize = p(GlobalAddrMap)("mem").size
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require(memSize % dut.io.mem_axi.size == 0)
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for (axi <- dut.io.mem_axi) {
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val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi.size))
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@ -6,7 +6,7 @@ import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule, LazyModuleImp}
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import uncore.tilelink2._
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import uncore.devices._
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import util.ParameterizedBundle
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import rocket._
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@ -14,18 +14,41 @@ import rocket.Util._
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import coreplex._
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// the following parameters will be refactored properly with TL2
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case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
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case object ConfigString extends Field[GlobalVariable[String]]
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case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
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case object GlobalAddrMap extends Field[AddrMap]
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case object ConfigString extends Field[String]
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case object NCoreplexExtClients extends Field[Int]
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
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/** Base Top with no Periphery */
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abstract class BaseTop(val p: Parameters) extends LazyModule {
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abstract class BaseTop(q: Parameters) extends LazyModule {
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// the following variables will be refactored properly with TL2
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val pInterrupts = new RangeManager
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val pBusMasters = new RangeManager
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val pDevices = new ResourceManager[AddrMapEntry]
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lazy val c = CoreplexConfig(
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nTiles = q(NTiles),
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nExtInterrupts = pInterrupts.sum,
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nSlaves = pBusMasters.sum,
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nMemChannels = q(NMemoryChannels),
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hasSupervisor = q(UseVM),
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hasExtMMIOPort = true
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)
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lazy val genGlobalAddrMap = GenerateGlobalAddrMap(q, pDevices.get)
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private val qWithMap = q.alterPartial({case GlobalAddrMap => genGlobalAddrMap})
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lazy val genConfigString = GenerateConfigString(qWithMap, c, pDevices.get)
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implicit val p = qWithMap.alterPartial({
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case ConfigString => genConfigString
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case NCoreplexExtClients => pBusMasters.sum})
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||||
// Add a peripheral bus
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val peripheryBus = LazyModule(new TLXbar)
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val legacy = LazyModule(new TLLegacy()(p.alterPartial({ case TLId => "L2toMMIO" })))
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||||
peripheryBus.node := TLBuffer(TLWidthWidget(TLHintHandler(legacy.node), legacy.tlDataBytes))
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}
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class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
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@ -35,24 +58,19 @@ class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBun
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class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
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||||
val outer: L = l
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||||
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||||
val c = CoreplexConfig(
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||||
nTiles = p(NTiles),
|
||||
nExtInterrupts = outer.pInterrupts.sum,
|
||||
nSlaves = outer.pBusMasters.sum,
|
||||
nMemChannels = p(NMemoryChannels),
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hasSupervisor = p(UseVM),
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hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty)
|
||||
)
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||||
val coreplex = p(BuildCoreplex)(p, outer.c)
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||||
val io: B = b(coreplex)
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||||
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||||
def genGlobalAddrMap = GenerateGlobalAddrMap(p, outer.pDevices.get)
|
||||
def genConfigString = GenerateConfigString(p, c, outer.pDevices.get)
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||||
io.success := coreplex.io.success
|
||||
|
||||
p(NCoreplexExtClients).assign(outer.pBusMasters.sum)
|
||||
p(GlobalAddrMap).assign(genGlobalAddrMap)
|
||||
p(ConfigString).assign(genConfigString)
|
||||
val mmioNetwork =
|
||||
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
|
||||
p.alterPartial({ case TLId => "L2toMMIO" })))
|
||||
mmioNetwork.io.in.head <> coreplex.io.master.mmio.get
|
||||
outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
|
||||
|
||||
println("Generated Address Map")
|
||||
for (entry <- p(GlobalAddrMap).get.flatten) {
|
||||
for (entry <- p(GlobalAddrMap).flatten) {
|
||||
val name = entry.name
|
||||
val start = entry.region.start
|
||||
val end = entry.region.start + entry.region.size - 1
|
||||
@ -60,36 +78,27 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
|
||||
}
|
||||
|
||||
println("Generated Configuration String")
|
||||
println(p(ConfigString).get)
|
||||
|
||||
val coreplex = p(BuildCoreplex)(p, c)
|
||||
val io: B = b(coreplex)
|
||||
|
||||
io.success := coreplex.io.success
|
||||
|
||||
val mmioNetwork = c.hasExtMMIOPort.option(
|
||||
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
|
||||
p.alterPartial({ case TLId => "L2toMMIO" }))))
|
||||
mmioNetwork.foreach { _.io.in.head <> coreplex.io.master.mmio.get }
|
||||
println(p(ConfigString))
|
||||
ConfigStringOutput.contents = Some(p(ConfigString))
|
||||
}
|
||||
|
||||
/** Example Top with Periphery */
|
||||
class ExampleTop(p: Parameters) extends BaseTop(p)
|
||||
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
|
||||
class ExampleTop(q: Parameters) extends BaseTop(q)
|
||||
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
|
||||
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
|
||||
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
|
||||
}
|
||||
|
||||
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
|
||||
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
|
||||
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
|
||||
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
|
||||
|
||||
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
|
||||
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
|
||||
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
|
||||
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
|
||||
|
||||
/** Example Top with TestRAM */
|
||||
class ExampleTopWithTestRAM(p: Parameters) extends ExampleTop(p)
|
||||
class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
|
||||
with PeripheryTestRAM {
|
||||
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
|
||||
}
|
||||
|
||||
@ -64,10 +64,8 @@ object GenerateGlobalAddrMap {
|
||||
new AddrMap(entries)
|
||||
}
|
||||
|
||||
lazy val extIOAddrMap = new AddrMap(
|
||||
pDevicesEntries ++ p(ExtMMIOPorts),
|
||||
start = BigInt("50000000", 16),
|
||||
collapse = true)
|
||||
lazy val tl2AddrMap = new AddrMap(pDevicesEntries, collapse = true)
|
||||
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: p(ExtMMIOPorts), collapse = true)
|
||||
|
||||
val memBase = 0x80000000L
|
||||
val memSize = p(ExtMemSize)
|
||||
@ -83,9 +81,9 @@ object GenerateGlobalAddrMap {
|
||||
|
||||
object GenerateConfigString {
|
||||
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
|
||||
val addrMap = p(GlobalAddrMap).get
|
||||
val addrMap = p(GlobalAddrMap)
|
||||
val plicAddr = addrMap("io:int:plic").start
|
||||
val prciAddr = addrMap("io:ext:prci").start
|
||||
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
|
||||
val xLen = p(XLen)
|
||||
val res = new StringBuilder
|
||||
res append "plic {\n"
|
||||
@ -94,7 +92,7 @@ object GenerateConfigString {
|
||||
res append s" ndevs ${c.plicKey.nDevices};\n"
|
||||
res append "};\n"
|
||||
res append "rtc {\n"
|
||||
res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
|
||||
res append s" addr 0x${clint.timeAddress.toString(16)};\n"
|
||||
res append "};\n"
|
||||
if (addrMap contains "mem") {
|
||||
res append "ram {\n"
|
||||
@ -117,8 +115,8 @@ object GenerateConfigString {
|
||||
res append s" $i {\n"
|
||||
res append " 0 {\n"
|
||||
res append s" isa $isa;\n"
|
||||
res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
|
||||
res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
|
||||
res append s" timecmp 0x${clint.timecmpAddress(i).toString(16)};\n"
|
||||
res append s" ipi 0x${clint.msipAddress(i).toString(16)};\n"
|
||||
res append s" plic {\n"
|
||||
res append s" m {\n"
|
||||
res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"
|
||||
@ -138,7 +136,7 @@ object GenerateConfigString {
|
||||
}
|
||||
res append "};\n"
|
||||
pDevicesEntries foreach { entry =>
|
||||
val region = addrMap("io:ext:" + entry.name)
|
||||
val region = addrMap("io:ext:TL2:" + entry.name)
|
||||
res append s"${entry.name} {\n"
|
||||
res append s" addr 0x${region.start.toString(16)};\n"
|
||||
res append s" size 0x${region.size.toString(16)}; \n"
|
||||
@ -158,8 +156,8 @@ object GenerateBootROM {
|
||||
|
||||
// for now, have the reset vector jump straight to memory
|
||||
val memBase = (
|
||||
if (p(GlobalAddrMap).get contains "mem") p(GlobalAddrMap).get("mem")
|
||||
else p(GlobalAddrMap).get("io:int:dmem0")
|
||||
if (p(GlobalAddrMap) contains "mem") p(GlobalAddrMap)("mem")
|
||||
else p(GlobalAddrMap)("io:int:dmem0")
|
||||
).start
|
||||
val resetToMemDist = memBase - p(ResetVector)
|
||||
require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
|
||||
@ -168,6 +166,6 @@ object GenerateBootROM {
|
||||
require(rom.getInt(12) == 0,
|
||||
"Config string address position should not be occupied by code")
|
||||
rom.putInt(12, configStringAddr)
|
||||
rom.array() ++ (p(ConfigString).get.getBytes.toSeq)
|
||||
rom.array() ++ (p(ConfigString).getBytes.toSeq)
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user