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Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor

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This commit is contained in:
Richard Xia
2016-09-16 17:10:52 -07:00
parent 851a336db4 4abba87b61
commit 63f13ae7ce
33 changed files with 632 additions and 337 deletions
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2
src/main/scala/groundtest/Comparator.scala
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@ -338,7 +338,7 @@ class ComparatorSink(implicit val p: Parameters) extends Module
assert (g.is_builtin_type, "grant not builtin")
assert (base.g_type === g.g_type, "g_type mismatch")
assert (base.addr_beat === g.addr_beat || !g.hasData(), "addr_beat mismatch")
assert (base.addr_beat === g.addr_beat || !g.hasMultibeatData(), "addr_beat mismatch")
assert (base.data === g.data || !g.hasData(), "data mismatch")
assert_conds.zipWithIndex.foreach { case (cond, i) =>

19
src/main/scala/groundtest/Configs.scala
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@ -92,7 +92,7 @@ class WithGroundTest extends Config(
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
@ -137,11 +137,11 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:ext:testram").map(name =>
site(GlobalAddrMap).get(name).start.longValue),
targets = Seq("mem", "io:ext:TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,
atomics = site(UseAtomics),
atomics = false, // !!! re-enable soon: site(UseAtomics),
prefetches = site("COMPARATOR_PREFETCHES"))
case FPUConfig => None
case UseAtomics => false
@ -168,7 +168,7 @@ class WithMemtest extends Config(
}
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
startAddress = site(GlobalAddrMap).get("mem").start)
startAddress = site(GlobalAddrMap)("mem").start)
case BuildGroundTest =>
(p: Parameters) => Module(new GeneratorTest()(p))
case _ => throw new CDEMatchError
@ -228,7 +228,7 @@ class WithNastiConverterTest extends Config(
}
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
startAddress = site(GlobalAddrMap).get("mem").start)
startAddress = site(GlobalAddrMap)("mem").start)
case BuildGroundTest =>
(p: Parameters) => Module(new NastiConverterTest()(p))
case _ => throw new CDEMatchError
@ -248,7 +248,7 @@ class WithTraceGen extends Config(
val nSets = 32 // L2 NSets
val nWays = 1
val blockOffset = site(CacheBlockOffsetBits)
val baseAddr = site(GlobalAddrMap).get("mem").start
val baseAddr = site(GlobalAddrMap)("mem").start
val nBeats = site(MIFDataBeats)
List.tabulate(4 * nWays) { i =>
Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
@ -260,6 +260,7 @@ class WithTraceGen extends Config(
knobValues = {
case "L1D_SETS" => 16
case "L1D_WAYS" => 1
case _ => throw new CDEMatchError
})
class WithPCIeMockupTest extends Config(
@ -270,7 +271,7 @@ class WithPCIeMockupTest extends Config(
GroundTestTileSettings(1))
case GeneratorKey => GeneratorParameters(
maxRequests = 128,
startAddress = site(GlobalAddrMap).get("mem").start)
startAddress = site(GlobalAddrMap)("mem").start)
case BuildGroundTest =>
(p: Parameters) => p(TileId) match {
case 0 => Module(new GeneratorTest()(p))
@ -304,7 +305,7 @@ class WithDirectComparator extends Config(
targets = Seq(0L, 0x100L),
width = 8,
operations = 1000,
atomics = site(UseAtomics),
atomics = false, // !!! re-enable soon: site(UseAtomics),
prefetches = site("COMPARATOR_PREFETCHES"))
case FPUConfig => None
case UseAtomics => false

2
src/main/scala/groundtest/Regression.scala
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@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:ext:bootrom").start)
io.cache.req.bits.addr := UInt(addrMap("io:ext:TL2:bootrom").start)
io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)