riscv/rocket-chip
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avoid reading data when write mask is full

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This commit is contained in:
Henry Cook
2015-03-17 20:28:06 -07:00
parent b9591b297c
commit 638bace858
2 changed files with 18 additions and 8 deletions
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7
uncore/src/main/scala/uncore.scala
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@ -150,8 +150,13 @@ abstract class XactTracker extends CoherenceAgentModule {
connectDataBeatCounter(in.fire(), in.bits.payload, UInt(0))._2
}
def addPendingBit[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[LogicalNetworkIO[T]]) = {
def addPendingBitWhenHasData[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[LogicalNetworkIO[T]]) = {
(Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.hasData()) &
UIntToOH(in.bits.payload.addr_beat))
}
def addPendingBitWhenWmaskIsNotFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
(Fill(in.bits.payload.tlDataBeats, in.fire() && !in.bits.payload.wmask().andR) &
UIntToOH(in.bits.payload.addr_beat))
}
}