Add support for L1 data scratchpads instead of caches

They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.

src/main/scala/rocket/tile.scala

@@ -5,6 +5,7 @@ package rocket
 import Chisel._
 import uncore.tilelink._
 import uncore.agents._
+import uncore.converters._
 import uncore.devices._
 import Util._
 import cde.{Parameters, Field}
@@ -31,6 +32,7 @@ abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
     val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
     val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
     val prci = new PRCITileIO().flip
+    val slave = (p(DataScratchpadSize) > 0).option(new ClientUncachedTileLinkIO().flip)
   }
 
   val io = new TileIO
@@ -121,6 +123,12 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
     core.io.ptw <> ptw.io.dpath
   }
 
+  io.slave foreach { case slavePort =>
+    val adapter = Module(new ScratchpadSlavePort()(dcacheParams))
+    adapter.io.tl <> TileLinkFragmenter(slavePort)
+    adapter.io.dmem +=: dcPorts
+  }
+
   require(dcPorts.size == core.dcacheArbPorts)
   val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
   dcArb.io.requestor <> dcPorts