riscv/rocket-chip
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Add support for L1 data scratchpads instead of caches

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They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).

They are currently limited to single cores without DRAM.  We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
This commit is contained in:
Andrew Waterman
2016-09-02 15:59:16 -07:00
parent dc9ae19936
commit 63679bb019
8 changed files with 140 additions and 36 deletions
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4
src/main/scala/rocket/rocket.scala
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@ -30,6 +30,7 @@ case object ResetVector extends Field[BigInt]
case object NBreakpoints extends Field[Int]
case object NPerfCounters extends Field[Int]
case object NPerfEvents extends Field[Int]
case object DataScratchpadSize extends Field[Int]
trait HasCoreParameters extends HasAddrMapParameters {
implicit val p: Parameters
@ -48,6 +49,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
val nBreakpoints = p(NBreakpoints)
val nPerfCounters = p(NPerfCounters)
val nPerfEvents = p(NPerfEvents)
val usingDataScratchpad = p(DataScratchpadSize) > 0
val retireWidth = p(RetireWidth)
val fetchWidth = p(FetchWidth)
@ -55,7 +57,7 @@ trait HasCoreParameters extends HasAddrMapParameters {
val coreInstBytes = coreInstBits/8
val coreDataBits = xLen
val coreDataBytes = coreDataBits/8
val dcacheArbPorts = 1 + (if (usingVM) 1 else 0) + p(BuildRoCC).size
val dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size
val coreDCacheReqTagBits = 6
val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)