From 6359ff96e5c308f9a1fdcfae3fe7ad843cff66b9 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 14 Apr 2017 15:25:51 +0900 Subject: [PATCH] Several ScratchpadSlavePort bug fixes (#676) * only replicate scratch slave d-channel resp when AMO req * dtim: port can't support put partial mask with holes * dtim: use \!isRead instead of isAMO * Fix ScratchpadSlavePort looking at wrong Acquire message Rename acq to a in the helper method. Delete isRead and isWrite altogether. --- .../scala/rocket/ScratchpadSlavePort.scala | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 0cf50a25..8aee7658 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -24,7 +24,7 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L executable = true, supportsArithmetic = if (usingAtomics) TransferSizes(1, coreDataBytes) else TransferSizes.none, supportsLogical = if (usingAtomics) TransferSizes(1, coreDataBytes) else TransferSizes.none, - supportsPutPartial = TransferSizes(1, coreDataBytes), + supportsPutPartial = TransferSizes.none, // Can't support PutPartial supportsPutFull = TransferSizes(1, coreDataBytes), supportsGet = TransferSizes(1, coreDataBytes), fifoId = Some(0))), // requests handled in FIFO order @@ -51,30 +51,27 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data } when (tl_in.a.fire()) { acq := tl_in.a.bits } - val isWrite = acq.opcode === TLMessages.PutFullData || acq.opcode === TLMessages.PutPartialData - val isRead = !edge.hasData(acq) - - def formCacheReq(acq: TLBundleA) = { + def formCacheReq(a: TLBundleA) = { val req = Wire(new HellaCacheReq) - req.cmd := MuxLookup(acq.opcode, Wire(M_XRD), Array( + req.cmd := MuxLookup(a.opcode, Wire(M_XRD), Array( TLMessages.PutFullData -> M_XWR, - TLMessages.PutPartialData -> M_XWR, - TLMessages.ArithmeticData -> MuxLookup(acq.param, Wire(M_XRD), Array( + TLMessages.ArithmeticData -> MuxLookup(a.param, Wire(M_XRD), Array( TLAtomics.MIN -> M_XA_MIN, TLAtomics.MAX -> M_XA_MAX, TLAtomics.MINU -> M_XA_MINU, TLAtomics.MAXU -> M_XA_MAXU, TLAtomics.ADD -> M_XA_ADD)), - TLMessages.LogicalData -> MuxLookup(acq.param, Wire(M_XRD), Array( + TLMessages.LogicalData -> MuxLookup(a.param, Wire(M_XRD), Array( TLAtomics.XOR -> M_XA_XOR, TLAtomics.OR -> M_XA_OR, TLAtomics.AND -> M_XA_AND, TLAtomics.SWAP -> M_XA_SWAP)), TLMessages.Get -> M_XRD)) // treat all loads as full words, so bytes appear in correct lane - req.typ := Mux(isRead, log2Ceil(coreDataBytes), acq.size) - req.addr := Mux(isRead, ~(~acq.address | (coreDataBytes-1)), acq.address) + req.typ := Mux(edge.hasData(a), a.size, log2Ceil(coreDataBytes)) + req.addr := Mux(edge.hasData(a), a.address, ~(~a.address | (coreDataBytes-1))) req.tag := UInt(0) + req.phys := true req } @@ -91,10 +88,11 @@ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends L // place AMO data in correct word lane val minAMOBytes = 4 val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data) - val alignedGrantData = Mux(acq.size <= log2Ceil(minAMOBytes), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData) + val alignedGrantData = + Mux(edge.hasData(acq) && (acq.size <= log2Ceil(minAMOBytes)), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData) tl_in.d.valid := io.dmem.resp.valid || state === s_grant - tl_in.d.bits := Mux(isWrite, + tl_in.d.bits := Mux(acq.opcode === TLMessages.PutFullData, edge.AccessAck(acq, UInt(0)), edge.AccessAck(acq, UInt(0), UInt(0))) tl_in.d.bits.data := alignedGrantData