1
0

minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)

This commit is contained in:
Rimas Avizienis 2013-01-23 19:27:53 -08:00
parent 6b00e7ff74
commit 63060bc0a8
3 changed files with 11 additions and 6 deletions

View File

@ -603,7 +603,10 @@ class Control(implicit conf: RocketConfiguration) extends Component
class Scoreboard class Scoreboard
{ {
val r = Reg(resetVal = Bits(0)) // val r = Reg(resetVal = Bits(0))
// RIMAS: explicitly set width to 32, otherwise Chisel would set it to 1024
// and cause a ton of warnings during synthesis
val r = Reg(resetVal = Bits(0,32))
var next = r var next = r
var ens = Bool(false) var ens = Bool(false)
def apply(addr: UFix) = r(addr) def apply(addr: UFix) = r(addr)

View File

@ -183,7 +183,8 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val tag = c.code.encode(s2_tag) val tag = c.code.encode(s2_tag)
tag_array.write(s2_idx, Fill(c.assoc, tag), wmask) tag_array.write(s2_idx, Fill(c.assoc, tag), wmask)
} }
/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM // /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) {
tag_rdata := tag_array(s0_pgoff(c.untagbits-1,c.offbits)) tag_rdata := tag_array(s0_pgoff(c.untagbits-1,c.offbits))
} }
@ -227,7 +228,8 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte
val d = io.mem.grant.bits.payload.data val d = io.mem.grant.bits.payload.data
data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d) data_array(Cat(s2_idx,rf_cnt)) := c.code.encode(d)
} }
/*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM // /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM
.elsewhen (s0_valid) {
s1_dout := data_array(s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth)) s1_dout := data_array(s0_pgoff(c.untagbits-1,c.offbits-rf_cnt.getWidth))
} }
// if s1_tag_match is critical, replace with partial tag check // if s1_tag_match is critical, replace with partial tag check

View File

@ -577,15 +577,15 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Component {
val tags = Mem(conf.sets, seqRead = true) { UFix(width = metabits*conf.ways) } val tags = Mem(conf.sets, seqRead = true) { UFix(width = metabits*conf.ways) }
val tag = Reg{UFix()} val tag = Reg{UFix()}
when (io.read.valid) {
tag := tags(io.read.bits.addr(conf.untagbits-1,conf.offbits))
}
when (rst || io.write.valid) { when (rst || io.write.valid) {
val addr = Mux(rst, rst_cnt, io.write.bits.idx) val addr = Mux(rst, rst_cnt, io.write.bits.idx)
val data = Cat(Mux(rst, conf.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag) val data = Cat(Mux(rst, conf.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag)
val mask = Mux(rst, Fix(-1), io.write.bits.way_en) val mask = Mux(rst, Fix(-1), io.write.bits.way_en)
tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask)) tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
} }
when (io.read.valid) {
tag := tags(io.read.bits.addr(conf.untagbits-1,conf.offbits))
}
for (w <- 0 until conf.ways) { for (w <- 0 until conf.ways) {
val m = tag(metabits*(w+1)-1, metabits*w) val m = tag(metabits*(w+1)-1, metabits*w)