riscv/rocket-chip
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)

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Rimas Avizienis
2013-01-23 19:27:53 -08:00
parent 6b00e7ff74
commit 63060bc0a8
3 changed files with 11 additions and 6 deletions
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6
rocket/src/main/scala/nbdcache.scala
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@ -577,15 +577,15 @@ class MetaDataArray(implicit conf: DCacheConfig) extends Component {
val tags = Mem(conf.sets, seqRead = true) { UFix(width = metabits*conf.ways) }
val tag = Reg{UFix()}
when (io.read.valid) {
tag := tags(io.read.bits.addr(conf.untagbits-1,conf.offbits))
}
when (rst || io.write.valid) {
val addr = Mux(rst, rst_cnt, io.write.bits.idx)
val data = Cat(Mux(rst, conf.co.newStateOnFlush, io.write.bits.data.state), io.write.bits.data.tag)
val mask = Mux(rst, Fix(-1), io.write.bits.way_en)
tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
}
when (io.read.valid) {
tag := tags(io.read.bits.addr(conf.untagbits-1,conf.offbits))
}
for (w <- 0 until conf.ways) {
val m = tag(metabits*(w+1)-1, metabits*w)