riscv/rocket-chip
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correctly initialize the active flag

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Yunsup Lee 2016-10-03 16:38:33 -07:00 committed by Yunsup Lee
parent 6ec2e7c5bd
commit 62954d543e
1 changed files with 1 additions and 1 deletions
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src/main/scala/util/Timer.scala
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@ -45,7 +45,7 @@ class SimpleTimer(initCount: Int) extends Module {
} }
val countdown = Reg(UInt(width = log2Up(initCount))) val countdown = Reg(UInt(width = log2Up(initCount)))
val active = Reg(Bool()) val active = Reg(init = Bool(false))
when (active) { countdown := countdown - UInt(1) } when (active) { countdown := countdown - UInt(1) }