riscv/rocket-chip
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Improved TileIO organization, beginnings of hub implementation

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Henry Cook committed 2012-02-22 18:24:52 -08:00
1 parent 24a32c2811
commit 62837537f4
2 files changed
+87 -6
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rocket/src/main/scala/consts.scala
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@@ -179,6 +179,7 @@ object Constants
val TILE_ID_BITS = 1
val TILE_XACT_ID_BITS = 1 // log2(NMSHR)
val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set
val NGLOBAL_XACTS = 1 << IDX_BITS
val TTYPE_BITS = 2
val X_READ_SHARED = UFix(0, TTYPE_BITS)