diff --git a/junctions/src/main/scala/addrmap.scala b/junctions/src/main/scala/addrmap.scala index 5fa34483..275314b5 100644 --- a/junctions/src/main/scala/addrmap.scala +++ b/junctions/src/main/scala/addrmap.scala @@ -16,7 +16,6 @@ case object PPNBits extends Field[Int] case object VPNBits extends Field[Int] case object GlobalAddrMap extends Field[AddrMap] -case object MMIOBase extends Field[BigInt] trait HasAddrMapParameters { implicit val p: Parameters @@ -30,12 +29,12 @@ trait HasAddrMapParameters { val pgLevelBits = p(PgLevelBits) val asIdBits = p(ASIdBits) - val addrMap = new AddrHashMap(p(GlobalAddrMap), p(MMIOBase)) + val addrMap = new AddrHashMap(p(GlobalAddrMap)) } abstract class MemRegion { def size: BigInt } -case class MemSize(size: BigInt, prot: Int) extends MemRegion +case class MemSize(size: BigInt, prot: Int, cacheable: Boolean = false) extends MemRegion case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion object AddrMapConsts { @@ -55,7 +54,7 @@ class AddrMapProt extends Bundle { case class AddrMapEntry(name: String, start: Option[BigInt], region: MemRegion) -case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int) +case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt, prot: Int, cacheable: Boolean) class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[AddrMapEntry] { @@ -65,17 +64,19 @@ class AddrMap(entries: Seq[AddrMapEntry]) extends scala.collection.IndexedSeq[Ad def countSlaves: Int = { this map { entry: AddrMapEntry => entry.region match { - case MemSize(_, _) => 1 + case MemSize(_, _, _) => 1 case MemSubmap(_, submap) => submap.countSlaves }} reduceLeft(_ + _) } + + override def tail: AddrMap = new AddrMap(entries.tail) } object AddrMap { def apply(elems: AddrMapEntry*): AddrMap = new AddrMap(elems) } -class AddrHashMap(addrmap: AddrMap, start: BigInt) { +class AddrHashMap(addrmap: AddrMap, start: BigInt = BigInt(0)) { val mapping = new HashMap[String, AddrHashMapEntry] private def genPairs(am: AddrMap, start: BigInt): Seq[(String, AddrHashMapEntry)] = { @@ -84,18 +85,18 @@ class AddrHashMap(addrmap: AddrMap, start: BigInt) { var pairs = Seq[(String, AddrHashMapEntry)]() am.foreach { case AddrMapEntry(name, startOpt, region) => region match { - case MemSize(size, prot) => { + case MemSize(size, prot, cacheable) => { if (!startOpt.isEmpty) base = startOpt.get - pairs = (name, AddrHashMapEntry(ind, base, size, prot)) +: pairs + pairs = (name, AddrHashMapEntry(ind, base, size, prot, cacheable)) +: pairs base += size ind += 1 } case MemSubmap(size, submap) => { if (!startOpt.isEmpty) base = startOpt.get val subpairs = genPairs(submap, base).map { - case (subname, AddrHashMapEntry(subind, subbase, subsize, prot)) => + case (subname, AddrHashMapEntry(subind, subbase, subsize, prot, cacheable)) => (name + ":" + subname, - AddrHashMapEntry(ind + subind, subbase, subsize, prot)) + AddrHashMapEntry(ind + subind, subbase, subsize, prot, cacheable)) } pairs = subpairs ++ pairs ind += subpairs.size @@ -111,17 +112,29 @@ class AddrHashMap(addrmap: AddrMap, start: BigInt) { def nEntries: Int = mapping.size def apply(name: String): AddrHashMapEntry = mapping(name) def get(name: String): Option[AddrHashMapEntry] = mapping.get(name) - def sortedEntries(): Seq[(String, BigInt, BigInt, Int)] = { - val arr = new Array[(String, BigInt, BigInt, Int)](mapping.size) - mapping.foreach { case (name, AddrHashMapEntry(port, base, size, prot)) => - arr(port) = (name, base, size, prot) + def sortedEntries(): Seq[(String, BigInt, BigInt, Int, Boolean)] = { + val arr = new Array[(String, BigInt, BigInt, Int, Boolean)](mapping.size) + mapping.foreach { case (name, AddrHashMapEntry(port, base, size, prot, cacheable)) => + arr(port) = (name, base, size, prot, cacheable) } arr.toSeq } + def isInRegion(name: String, addr: UInt): Bool = { + val start = mapping(name).start + val size = mapping(name).size + UInt(start) <= addr && addr < UInt(start + size) + } + + def isCacheable(addr: UInt): Bool = { + sortedEntries().map { case (_, base, size, _, cacheable) => + UInt(base) <= addr && addr < UInt(base + size) && Bool(cacheable) + }.reduce(_ || _) + } + def isValid(addr: UInt): Bool = { addr < UInt(start) || sortedEntries().map { - case (_, base, size, _) => + case (_, base, size, _, _) => addr >= UInt(base) && addr < UInt(base + size) }.reduceLeft(_ || _) } @@ -129,7 +142,7 @@ class AddrHashMap(addrmap: AddrMap, start: BigInt) { def getProt(addr: UInt): AddrMapProt = { val protBits = Mux(addr < UInt(start), Bits(AddrMapConsts.RWX, 3), - Mux1H(sortedEntries().map { case (_, base, size, prot) => + Mux1H(sortedEntries().map { case (_, base, size, prot, _) => (addr >= UInt(base) && addr < UInt(base + size), Bits(prot, 3)) })) new AddrMapProt().fromBits(protBits) diff --git a/junctions/src/main/scala/nasti.scala b/junctions/src/main/scala/nasti.scala index cc2a3a98..cbb6e729 100644 --- a/junctions/src/main/scala/nasti.scala +++ b/junctions/src/main/scala/nasti.scala @@ -534,7 +534,7 @@ class NastiRecursiveInterconnect( addrmap.zip(realAddrMap).zip(xbar.io.slaves).zipWithIndex.foreach { case (((entry, (start, size)), xbarSlave), i) => { entry.region match { - case MemSize(_, _) => + case MemSize(_, _, _) => io.slaves(slaveInd) <> xbarSlave slaveInd += 1 case MemSubmap(_, submap) =>