Wesley W. Terpstra
GitHub
commit
625919722c
@ -43,10 +43,6 @@ case class AHBSlavePortParameters(
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// Check that the link can be implemented in AHB
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require (maxTransfer <= beatBytes * AHBParameters.maxTransfer)
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lazy val routingMask = AddressDecoder(slaves.map(_.address))
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def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
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// Require disjoint ranges for addresses
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slaves.combinations(2).foreach { case Seq(x,y) =>
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x.address.foreach { a => y.address.foreach { b =>
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@ -16,10 +16,10 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter
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new AHBRegBundle((), _) with RRTest1Bundle)(
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new AHBRegModule((), _, _) with RRTest1Module)
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class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
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class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
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val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
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var xbar = LazyModule(new AHBFanout)
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val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
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val gpio = LazyModule(new RRTest0(0x100))
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@ -34,6 +34,67 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
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}
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}
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class AHBNativeTest()(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzNative).module)
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io.finished := dut.io.finished
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}
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class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule
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{
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val node = AHBOutputNode()
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
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model.node := fuzz.node
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node :=
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TLToAHB()(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val out = node.bundleOut
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val finished = Bool(OUTPUT)
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}
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io.finished := fuzz.module.io.finished
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}
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}
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class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
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{
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val node = AHBInputNode()
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val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.2)(
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AHBToTL()(
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node)))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
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{
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val master = LazyModule(new AHBFuzzMaster)
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val slave = LazyModule(new AHBFuzzSlave)
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slave.node := master.node
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := master.module.io.finished
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}
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}
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class AHBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzBridge).module)
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io.finished := dut.io.finished
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139
src/main/scala/uncore/ahb/ToTL.scala
Normal file
139
src/main/scala/uncore/ahb/ToTL.scala
Normal file
@ -0,0 +1,139 @@
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// See LICENSE.SiFive for license details.
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package uncore.ahb
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import config._
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import diplomacy._
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import uncore.tilelink2._
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case class AHBToTLNode() extends MixedAdapterNode(AHBImp, TLImp)(
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dFn = { case AHBMasterPortParameters(masters) =>
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TLClientPortParameters(clients = masters.map { m =>
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TLClientParameters(nodePath = m.nodePath)
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})
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},
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uFn = { mp => AHBSlavePortParameters(
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slaves = mp.managers.map { m =>
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def adjust(x: TransferSizes) = {
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if (x.contains(mp.beatBytes)) {
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TransferSizes(x.min, m.minAlignment.min(mp.beatBytes * AHBParameters.maxTransfer).toInt)
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} else { // larger than beatBytes requires beatBytes if misaligned
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x.intersect(TransferSizes(1, mp.beatBytes))
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}
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}
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AHBSlaveParameters(
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address = m.address,
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resources = m.resources,
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regionType = m.regionType,
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executable = m.executable,
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nodePath = m.nodePath,
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supportsWrite = adjust(m.supportsPutFull),
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supportsRead = adjust(m.supportsGet))},
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beatBytes = mp.beatBytes)
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})
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class AHBToTL()(implicit p: Parameters) extends LazyModule
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{
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val node = AHBToTLNode()
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val beatBytes = edgeOut.manager.beatBytes
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val d_send = RegInit(Bool(false))
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val d_recv = RegInit(Bool(false))
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val d_error = RegInit(Bool(false))
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val d_pause = RegInit(Bool(false))
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val d_write = RegInit(Bool(false))
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val d_addr = Reg(in.haddr)
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val d_size = Reg(in.hsize)
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when (out.d.valid) { d_recv := Bool(false); d_error := d_error || out.d.bits.error }
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when (out.a.ready) { d_send := Bool(false) }
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val a_count = RegInit(UInt(0, width = 4))
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val a_first = a_count === UInt(0)
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val d_last = a_first
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val burst_sizes = Seq(1, 1, 4, 4, 8, 8, 16, 16)
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val a_burst_size = Vec(burst_sizes.map(beats => UInt(log2Ceil(beats * beatBytes))))(in.hburst)
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val a_burst_mask = Vec(burst_sizes.map(beats => UInt(beats * beatBytes - 1)))(in.hburst)
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val a_burst_ok =
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in.htrans === AHBParameters.TRANS_NONSEQ && // only start burst on first AHB beat
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in.hsize === UInt(log2Ceil(beatBytes)) && // not a narrow burst
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(in.haddr & a_burst_mask) === UInt(0) && // address aligned to burst size
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in.hburst =/= AHBParameters.BURST_INCR && // we know the burst length a priori
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Mux(in.hwrite, // target device supports the burst
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edgeOut.manager.supportsPutFullSafe(in.haddr, a_burst_size),
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edgeOut.manager.supportsGetSafe (in.haddr, a_burst_size))
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val beat = TransferSizes(1, beatBytes)
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val a_legal = // Is the single-beat access allowed?
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Mux(in.hwrite,
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edgeOut.manager.supportsPutFullSafe(in.haddr, in.hsize, Some(beat)),
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edgeOut.manager.supportsGetSafe (in.haddr, in.hsize, Some(beat)))
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val a_access = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ
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val a_accept = in.hready && in.hsel && a_access
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when (a_accept) {
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a_count := a_count - UInt(1)
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d_error := d_error || !a_legal
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when ( in.hwrite) { d_send := Bool(true) }
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when (!in.hwrite) { d_recv := Bool(true) }
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when (a_first) {
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a_count := Mux(a_burst_ok, a_burst_mask >> log2Ceil(beatBytes), UInt(0))
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d_send := a_legal
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d_recv := a_legal
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d_error := !a_legal
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d_pause := Bool(false)
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d_write := in.hwrite
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d_addr := in.haddr
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d_size := Mux(a_burst_ok, a_burst_size, in.hsize)
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}
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}
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out.a.valid := d_send
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out.a.bits.opcode := Mux(d_write, TLMessages.PutFullData, TLMessages.Get)
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out.a.bits.param := UInt(0)
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out.a.bits.size := d_size
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out.a.bits.source := UInt(0)
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out.a.bits.address := d_addr
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out.a.bits.data := in.hwdata
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out.a.bits.mask := maskGen(d_addr, d_size, beatBytes)
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// Save the error for the last beat (so the master can't cancel the burst)
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// When we report an error, we need to be hreadyout LOW for one cycle
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val inject_error = d_last && (d_error || (out.d.valid && out.d.bits.error))
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when (inject_error) { d_pause := Bool(true) }
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out.d.ready := d_recv // backpressure AccessAckData arriving faster than AHB beats
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in.hrdata := out.d.bits.data
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in.hresp := inject_error
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in.hreadyout := (!inject_error || d_pause) && Mux(d_write, (!d_send || out.a.ready) && (!d_last || !d_recv || out.d.valid), out.d.valid || !d_recv)
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// Unused channels
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object AHBToTL
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{
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def apply()(x: AHBOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val tl = LazyModule(new AHBToTL)
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tl.node := x
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tl.node
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}
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}
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@ -25,9 +25,14 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
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val gpio = LazyModule(new RRTest0(0x100))
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model.node := fuzz.node
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xbar.node := TLToAPB()(TLDelayer(0.1)(model.node))
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ram.node := xbar.node
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gpio.node := xbar.node
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xbar.node :=
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TLToAPB()(
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TLDelayer(0.2)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(model.node)
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
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gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
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@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(model.node)
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
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gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
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@ -69,7 +69,12 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
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model.node := fuzz.node
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node := TLToAXI4(4)(TLDelayer(0.1)(model.node))
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node :=
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TLToAXI4(4)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.1)(
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model.node))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -84,9 +89,16 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4InputNode()
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
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val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
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ram.node := TLFragmenter(4, 16)(AXI4ToTL()(AXI4Fragmenter()(node)))
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.1)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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node))))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -8,18 +8,37 @@ import config._
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import diplomacy._
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import scala.math.{min,max}
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// pipe is only used if a queue has depth = 1
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class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
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case class TLBufferParams(depth: Int, flow: Boolean, pipe: Boolean)
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{
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require (a >= 0)
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require (b >= 0)
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require (c >= 0)
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require (d >= 0)
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require (e >= 0)
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require (depth >= 0)
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def isDefined = depth > 0
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def latency = if (isDefined && !flow) 1 else 0
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}
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object TLBufferParams
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{
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implicit def apply(depth: Int): TLBufferParams = TLBufferParams(depth, false, false)
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val default = TLBufferParams(2)
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val none = TLBufferParams(0)
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val flow = TLBufferParams(1, true, false)
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val pipe = TLBufferParams(1, false, true)
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}
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class TLBuffer(
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a: TLBufferParams,
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b: TLBufferParams,
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c: TLBufferParams,
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d: TLBufferParams,
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e: TLBufferParams)(implicit p: Parameters) extends LazyModule
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{
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def this(ace: TLBufferParams, bd: TLBufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
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def this(abcde: TLBufferParams)(implicit p: Parameters) = this(abcde, abcde)
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def this()(implicit p: Parameters) = this(TLBufferParams.default)
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val node = TLAdapterNode(
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clientFn = { p => p.copy(minLatency = p.minLatency + min(1,b) + min(1,c)) },
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managerFn = { p => p.copy(minLatency = p.minLatency + min(1,a) + min(1,d)) })
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clientFn = { p => p.copy(minLatency = p.minLatency + b.latency + c.latency) },
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managerFn = { p => p.copy(minLatency = p.minLatency + a.latency + d.latency) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -27,14 +46,22 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
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val out = node.bundleOut
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}
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def buffer[T <: Data](config: TLBufferParams, data: DecoupledIO[T]): DecoupledIO[T] = {
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if (config.isDefined) {
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Queue(data, config.depth, pipe=config.pipe, flow=config.flow)
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} else {
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data
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}
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}
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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if (a>0) { out.a <> Queue(in .a, a, pipe && a<2) } else { out.a <> in.a }
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if (d>0) { in .d <> Queue(out.d, d, pipe && d<2) } else { in.d <> out.d }
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out.a <> buffer(a, in .a)
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in .d <> buffer(d, out.d)
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if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
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if (b>0) { in .b <> Queue(out.b, b, pipe && b<2) } else { in.b <> out.b }
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if (c>0) { out.c <> Queue(in .c, c, pipe && c<2) } else { out.c <> in.c }
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if (e>0) { out.e <> Queue(in .e, e, pipe && e<2) } else { out.e <> in.e }
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in .b <> buffer(b, out.b)
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out.c <> buffer(c, in .c)
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out.e <> buffer(e, in .e)
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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@ -50,13 +77,16 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
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object TLBuffer
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{
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// applied to the TL source node; y.node := TLBuffer(x.node)
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def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x)
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def apply(entries: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x)
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def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x)
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def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x)
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def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x)
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def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val buffer = LazyModule(new TLBuffer(a, b, c, d, e, pipe))
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def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(TLBufferParams.default)(x)
|
||||
def apply(abcde: TLBufferParams) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
|
||||
def apply(ace: TLBufferParams, bd: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
|
||||
def apply(
|
||||
a: TLBufferParams,
|
||||
b: TLBufferParams,
|
||||
c: TLBufferParams,
|
||||
d: TLBufferParams,
|
||||
e: TLBufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
|
||||
buffer.node := x
|
||||
buffer.node
|
||||
}
|
||||
|
||||
@ -118,37 +118,40 @@ case class TLManagerPortParameters(
|
||||
// Does this Port manage this ID/address?
|
||||
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
|
||||
|
||||
private def safe_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
|
||||
val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
|
||||
if (allSame) containsSafe(address) && member(managers(0)).containsLg(lgSize) else {
|
||||
Mux1H(findSafe(address), managers.map(member(_).containsLg(lgSize)))
|
||||
}
|
||||
}
|
||||
private def fast_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
|
||||
val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
|
||||
if (allSame) member(managers(0)).containsLg(lgSize) else {
|
||||
Mux1H(findFast(address), managers.map(member(_).containsLg(lgSize)))
|
||||
}
|
||||
private def supportHelper(
|
||||
safe: Boolean,
|
||||
member: TLManagerParameters => TransferSizes,
|
||||
address: UInt,
|
||||
lgSize: UInt,
|
||||
range: Option[TransferSizes]): Bool = {
|
||||
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
|
||||
val supportCases = managers.groupBy(m => trim(member(m))).mapValues(_.flatMap(_.address))
|
||||
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.values.toList)
|
||||
val simplified = supportCases.mapValues(seq => AddressSet.unify(seq.map(_.widen(~mask)).distinct))
|
||||
simplified.map { case (s, a) =>
|
||||
(Bool(Some(s) == range) || s.containsLg(lgSize)) &&
|
||||
a.map(_.contains(address)).reduce(_||_)
|
||||
}.foldLeft(Bool(false))(_||_)
|
||||
}
|
||||
|
||||
// Check for support of a given operation at a specific address
|
||||
val supportsAcquireTSafe = safe_helper(_.supportsAcquireT) _
|
||||
val supportsAcquireBSafe = safe_helper(_.supportsAcquireB) _
|
||||
val supportsArithmeticSafe = safe_helper(_.supportsArithmetic) _
|
||||
val supportsLogicalSafe = safe_helper(_.supportsLogical) _
|
||||
val supportsGetSafe = safe_helper(_.supportsGet) _
|
||||
val supportsPutFullSafe = safe_helper(_.supportsPutFull) _
|
||||
val supportsPutPartialSafe = safe_helper(_.supportsPutPartial) _
|
||||
val supportsHintSafe = safe_helper(_.supportsHint) _
|
||||
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsAcquireT, address, lgSize, range)
|
||||
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsAcquireB, address, lgSize, range)
|
||||
def supportsArithmeticSafe(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsArithmetic, address, lgSize, range)
|
||||
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsLogical, address, lgSize, range)
|
||||
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsGet, address, lgSize, range)
|
||||
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsPutFull, address, lgSize, range)
|
||||
def supportsPutPartialSafe(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsPutPartial, address, lgSize, range)
|
||||
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(true, _.supportsHint, address, lgSize, range)
|
||||
|
||||
val supportsAcquireTFast = fast_helper(_.supportsAcquireT) _
|
||||
val supportsAcquireBFast = fast_helper(_.supportsAcquireB) _
|
||||
val supportsArithmeticFast = fast_helper(_.supportsArithmetic) _
|
||||
val supportsLogicalFast = fast_helper(_.supportsLogical) _
|
||||
val supportsGetFast = fast_helper(_.supportsGet) _
|
||||
val supportsPutFullFast = fast_helper(_.supportsPutFull) _
|
||||
val supportsPutPartialFast = fast_helper(_.supportsPutPartial) _
|
||||
val supportsHintFast = fast_helper(_.supportsHint) _
|
||||
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsAcquireT, address, lgSize, range)
|
||||
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsAcquireB, address, lgSize, range)
|
||||
def supportsArithmeticFast(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsArithmetic, address, lgSize, range)
|
||||
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsLogical, address, lgSize, range)
|
||||
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsGet, address, lgSize, range)
|
||||
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutFull, address, lgSize, range)
|
||||
def supportsPutPartialFast(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutPartial, address, lgSize, range)
|
||||
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsHint, address, lgSize, range)
|
||||
}
|
||||
|
||||
case class TLClientParameters(
|
||||
|
||||
83
src/main/scala/uncore/tilelink2/TestRAM.scala
Normal file
83
src/main/scala/uncore/tilelink2/TestRAM.scala
Normal file
@ -0,0 +1,83 @@
|
||||
// See LICENSE.SiFive for license details.
|
||||
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import util._
|
||||
|
||||
// Do not use this for synthesis! Only for simulation.
|
||||
class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val device = new MemoryDevice
|
||||
|
||||
val node = TLManagerNode(Seq(TLManagerPortParameters(
|
||||
Seq(TLManagerParameters(
|
||||
address = List(address),
|
||||
resources = device.reg,
|
||||
regionType = RegionType.UNCACHED,
|
||||
executable = executable,
|
||||
supportsGet = TransferSizes(1, beatBytes),
|
||||
supportsPutPartial = TransferSizes(1, beatBytes),
|
||||
supportsPutFull = TransferSizes(1, beatBytes),
|
||||
fifoId = Some(0))), // requests are handled in order
|
||||
beatBytes = beatBytes)))
|
||||
|
||||
// We require the address range to include an entire beat (for the write mask)
|
||||
require ((address.mask & (beatBytes-1)) == beatBytes-1)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
}
|
||||
|
||||
def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
|
||||
if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
|
||||
val mask = bigBits(address.mask >> log2Ceil(beatBytes))
|
||||
|
||||
val in = io.in(0)
|
||||
val edge = node.edgesIn(0)
|
||||
|
||||
val addrBits = (mask zip edge.addr_hi(in.a.bits).toBools).filter(_._1).map(_._2)
|
||||
val memAddress = Cat(addrBits.reverse)
|
||||
val mem = Mem(1 << addrBits.size, Vec(beatBytes, Bits(width = 8)))
|
||||
|
||||
// "Flow control"
|
||||
in.a.ready := in.d.ready
|
||||
in.d.valid := in.a.valid
|
||||
|
||||
val hasData = edge.hasData(in.a.bits)
|
||||
val wdata = Vec.tabulate(beatBytes) { i => in.a.bits.data(8*(i+1)-1, 8*i) }
|
||||
|
||||
in.d.bits := edge.AccessAck(in.a.bits, UInt(0))
|
||||
in.d.bits.data := Cat(mem(memAddress).reverse)
|
||||
in.d.bits.opcode := Mux(hasData, TLMessages.AccessAck, TLMessages.AccessAckData)
|
||||
when (in.a.fire() && hasData) { mem.write(memAddress, wdata, in.a.bits.mask.toBools) }
|
||||
|
||||
// Tie off unused channels
|
||||
in.b.valid := Bool(false)
|
||||
in.c.ready := Bool(true)
|
||||
in.e.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
|
||||
/** Synthesizeable unit testing */
|
||||
import unittest._
|
||||
|
||||
class TLRAMZeroDelay(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := TLDelayer(0.25)(model.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
|
||||
io.finished := fuzz.module.io.finished
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMZeroDelayTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMZeroDelay(ramBeatBytes)).module).io.finished
|
||||
}
|
||||
@ -13,6 +13,7 @@ class WithUncoreUnitTests extends Config((site, here, up) => {
|
||||
Seq(
|
||||
Module(new uncore.tilelink2.TLFuzzRAMTest),
|
||||
Module(new uncore.ahb.AHBBridgeTest),
|
||||
Module(new uncore.ahb.AHBNativeTest),
|
||||
Module(new uncore.apb.APBBridgeTest),
|
||||
Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4FullFuzzRAMTest),
|
||||
@ -28,6 +29,7 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
|
||||
Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
|
||||
Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
|
||||
Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
|
||||
Module(new uncore.tilelink2.TLRAMZeroDelayTest(4)),
|
||||
Module(new uncore.tilelink2.TLRR0Test),
|
||||
Module(new uncore.tilelink2.TLRR1Test),
|
||||
Module(new uncore.tilelink2.TLRAMRationalCrossingTest),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user