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tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111)

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Wesley W. Terpstra 2017-11-14 17:49:10 -08:00 committed by GitHub
parent 8b79f0394e
commit 61ef560c75
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5 changed files with 19 additions and 6 deletions

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@ -15,7 +15,6 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
require (concurrency >= 1) require (concurrency >= 1)
val node = TLAdapterNode( val node = TLAdapterNode(
clientFn = { case cp => require (!cp.unsafeAtomics); cp.copy(unsafeAtomics = true) },
managerFn = { case mp => mp.copy(managers = mp.managers.map { m => managerFn = { case mp => mp.copy(managers = mp.managers.map { m =>
val ourSupport = TransferSizes(1, mp.beatBytes) val ourSupport = TransferSizes(1, mp.beatBytes)
def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
@ -32,6 +31,13 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
val managers = edgeOut.manager.managers val managers = edgeOut.manager.managers
val beatBytes = edgeOut.manager.beatBytes val beatBytes = edgeOut.manager.beatBytes
// This is necessary (though not sufficient) for correctness:
edgeOut.manager.findTreeViolation() match {
case None => ()
case Some(node) => require(edgeOut.manager.isTree, s"AtomicAutomata can only be placed infront of a tree of diplomatic nodes (${node.name} has parents ${node.inputs.map(_._1.name)})")
}
// You also need to know that the slaves don't have an internal masters that can get between the read and write
// To which managers are we adding atomic support? // To which managers are we adding atomic support?
val ourSupport = TransferSizes(1, edgeOut.manager.beatBytes) val ourSupport = TransferSizes(1, edgeOut.manager.beatBytes)
val managersNeedingHelp = managers.filter { m => val managersNeedingHelp = managers.filter { m =>

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@ -67,6 +67,13 @@ case class TLManagerParameters(
c = regionType >= RegionType.UNCACHED, c = regionType >= RegionType.UNCACHED,
a = supportsArithmetic && supportsLogical)) a = supportsArithmetic && supportsLogical))
} }
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
} }
case class TLManagerPortParameters( case class TLManagerPortParameters(
@ -170,6 +177,9 @@ case class TLManagerPortParameters(
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutFull, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutFull, address, lgSize, range)
def supportsPutPartialFast(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutPartial, address, lgSize, range) def supportsPutPartialFast(address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsPutPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsHint, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = supportHelper(false, _.supportsHint, address, lgSize, range)
def findTreeViolation() = managers.flatMap(_.findTreeViolation()).headOption
def isTree = !managers.exists(!_.isTree)
} }
case class TLClientParameters( case class TLClientParameters(
@ -208,7 +218,6 @@ case class TLClientParameters(
case class TLClientPortParameters( case class TLClientPortParameters(
clients: Seq[TLClientParameters], clients: Seq[TLClientParameters],
unsafeAtomics: Boolean = false,
minLatency: Int = 0) // Only applies to B=>C minLatency: Int = 0) // Only applies to B=>C
{ {
require (!clients.isEmpty) require (!clients.isEmpty)

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@ -11,7 +11,7 @@ import scala.math.{min, max}
import AHBParameters._ import AHBParameters._
case class TLToAHBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImp)( case class TLToAHBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImp)(
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) => dFn = { case TLClientPortParameters(clients, minLatency) =>
val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) } val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
AHBMasterPortParameters(masters) AHBMasterPortParameters(masters)
}, },

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@ -10,7 +10,7 @@ import scala.math.{min, max}
import APBParameters._ import APBParameters._
case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)( case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)(
dFn = { case TLClientPortParameters(clients, unsafeAtomics, minLatency) => dFn = { case TLClientPortParameters(clients, minLatency) =>
val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) } val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
APBMasterPortParameters(masters) APBMasterPortParameters(masters)
}, },

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@ -34,8 +34,6 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
numClientPorts = 1 to 999, numClientPorts = 1 to 999,
numManagerPorts = 1 to 999, numManagerPorts = 1 to 999,
clientFn = { seq => clientFn = { seq =>
require (!seq.exists(_.unsafeAtomics) || seq.size == 1,
"An unsafe atomic port can not be combined with any other!")
seq(0).copy( seq(0).copy(
minLatency = seq.map(_.minLatency).min, minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>