From 61c39da4753baabffbbfd179fce395df5c89cf73 Mon Sep 17 00:00:00 2001 From: Richard Xia Date: Thu, 15 Jun 2017 19:49:59 -0700 Subject: [PATCH] Check for rvc before declaring illegal instruction after an ebreak. --- src/main/scala/rocket/Rocket.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/Rocket.scala b/src/main/scala/rocket/Rocket.scala index 57a93acf..2d146f7f 100644 --- a/src/main/scala/rocket/Rocket.scala +++ b/src/main/scala/rocket/Rocket.scala @@ -212,7 +212,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') || id_ctrl.rocc && csr.io.decode.rocc_illegal || id_csr_en && (csr.io.decode.read_illegal || !id_csr_ren && csr.io.decode.write_illegal) || - (id_sfence || id_system_insn) && csr.io.decode.system_illegal + !ibuf.io.inst(0).bits.rvc && ((id_sfence || id_system_insn) && csr.io.decode.system_illegal) // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25)