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axi4: get unit tests legal again

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This commit is contained in:
Wesley W. Terpstra 2017-04-21 17:13:51 -07:00
parent bf5cb396b9
commit 61a6f94196
1 changed files with 15 additions and 8 deletions
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23
src/main/scala/uncore/axi4/Test.scala
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@ -26,8 +26,8 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4Fragmenter()(TLToAXI4(0, true )(xbar.node))
gpio.node := AXI4Fragmenter()(TLToAXI4(0, false)(xbar.node))
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(0, true )(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(0, false)(xbar.node)))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished
@ -49,8 +49,8 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
ram.node := AXI4Fragmenter()(TLToAXI4(4,false)(xbar.node))
gpio.node := AXI4Fragmenter()(TLToAXI4(4,true )(xbar.node))
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,false)(xbar.node)))
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(4,true )(xbar.node)))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished
@ -70,11 +70,13 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node
node :=
// AXI4UserYanker()( ... once TLToAXI is updated
AXI4Deinterleaver(64)(
TLToAXI4(4)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
model.node))))
model.node)))))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@ -89,17 +91,22 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
{
val node = AXI4InputNode()
val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff))))
ram.node :=
TLFragmenter(4, 16)(
ram.node := TLFragmenter(4, 16)(xbar.node)
error.node := TLFragmenter(4, 16)(xbar.node)
xbar.node :=
TLFIFOFixer()(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
AXI4ToTL()(
AXI4UserYanker(4)(
AXI4Fragmenter()(
AXI4IdIndexer(4)(
AXI4IdIndexer(2)(
node))))))))
lazy val module = new LazyModuleImp(this) {