Added coherence tile function defs, with traits and constants
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128
rocket/src/main/scala/coherence.scala
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128
rocket/src/main/scala/coherence.scala
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package Top {
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import Chisel._
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import Constants._
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class TransactionInit extends Bundle {
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val ttype = Bits(width = 2)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionAbort extends Bundle {
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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}
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class ProbeRequest extends Bundle {
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val ptype = Bits(width = 2)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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}
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class ProbeReply extends Bundle {
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val ptype = Bits(width = 2)
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val hasData = Bool()
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionReply extends Bundle {
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val ttype = Bits(width = 2)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionFinish extends Bundle {
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ioTileLink extends Bundle {
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val xact_init = new TransactionInit().asOutput
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val xact_abort = new TransactionAbort().asInput
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val probe_req = new ProbeRequest().asInput
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val probe_rep = new ProbeReply().asOutput
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val xact_rep = new TransactionReply().asInput
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val xact_finish = new TransactionFinish().asOutput
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}
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trait ThreeStateIncoherence {
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val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
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def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
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val store = (cmd === M_XWR)
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val load = (cmd === M_XRD)
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val amo = cmd(3).toBool
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val read = load || amo || (cmd === M_PFR)
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val write = store || amo || (cmd === M_PFW)
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(read, write)
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}
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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( state === tileClean || state === tileDirty)
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}
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileDirty
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}
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def newStateOnWriteback() = tileInvalid
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def newStateOnFlush() = tileInvalid
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def newState(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), tileInvalid))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid)
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, state)
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}
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}
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trait FourStateCoherence {
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val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
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val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
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val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val is_hit = Bool(false)
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switch(cmd) {
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is(M_XRD) {
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is_hit := state === tileShared ||
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state === tileExclusiveClean ||
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state === tileExclusiveDirty
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}
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is(M_XWR) {
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is_hit := state === tileExclusiveClean ||
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state === tileExclusiveDirty
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}
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}
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is_hit
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}
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def needsWriteback (state: UFix): Bool = {
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state === tileExclusiveDirty
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}
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def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
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def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {
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val state = UFix(0)
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switch(incoming.ptype) {
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is(probeInvalidate) { state := tileInvalid }
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is(probeDowngrade) { state := tileShared }
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}
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state.toBits
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}
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}
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}
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@ -160,7 +160,7 @@ object Constants
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val ASID_BITS = 7;
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val PERM_BITS = 6;
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// rocketNBDCacheDM parameters
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// rocketNBDCache parameters
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val CPU_DATA_BITS = 64;
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val CPU_TAG_BITS = 9;
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val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
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@ -174,6 +174,10 @@ object Constants
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val NWAYS = 1;
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require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
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// coherence parameters
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val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
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val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
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// external memory interface
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val IMEM_TAG_BITS = 1;
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val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;
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