riscv/rocket-chip
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Added coherence tile function defs, with traits and constants

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This commit is contained in:
Henry Cook
2012-02-14 15:51:32 -08:00
parent 1b5e39e7fc
commit 619929eba1
2 changed files with 133 additions and 1 deletions
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6
rocket/src/main/scala/consts.scala
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@ -160,7 +160,7 @@ object Constants
val ASID_BITS = 7;
val PERM_BITS = 6;
// rocketNBDCacheDM parameters
// rocketNBDCache parameters
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 9;
val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
@ -174,6 +174,10 @@ object Constants
val NWAYS = 1;
require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
// coherence parameters
val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
// external memory interface
val IMEM_TAG_BITS = 1;
val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;