unify cache backend interfaces; generify arbiter
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7034c9be65
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6135615104
@ -18,74 +18,48 @@ class ioMem() extends Bundle
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val resp_data = Bits(MEM_DATA_BITS, INPUT);
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}
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class ioMemArbiter extends Bundle() {
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class ioMemArbiter(n: Int) extends Bundle() {
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val mem = new ioMem();
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val dcache = new ioDCache();
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// val icache = new ioICache();
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val icache = new ioIPrefetcherMem().flip();
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val vicache = new ioICache();
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val htif = new ioDCache();
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val requestor = Vec(n) { new ioDCache() }
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}
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class rocketMemArbiter extends Component {
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val io = new ioMemArbiter();
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class rocketMemArbiter(n: Int) extends Component {
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val io = new ioMemArbiter(n);
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require(io.mem.req_tag.getWidth >= log2up(n) + io.requestor(0).req_tag.getWidth)
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// *****************************
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// Interface to memory
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// *****************************
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var req_val = Bool(false)
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var req_rdy = io.mem.req_rdy
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for (i <- 0 until n)
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{
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io.requestor(i).req_rdy := req_rdy
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req_val = req_val || io.requestor(i).req_val
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req_rdy = req_rdy && !io.requestor(i).req_val
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}
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// Memory request is valid if either icache or dcache have a valid request
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io.mem.req_val := io.icache.req_val || io.vicache.req_val || io.dcache.req_val || io.htif.req_val
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var req_rw = io.requestor(n-1).req_rw
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var req_addr = io.requestor(n-1).req_addr
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var req_wdata = io.requestor(n-1).req_wdata
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var req_tag = Cat(io.requestor(n-1).req_tag, UFix(n-1, log2up(n)))
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for (i <- n-1 to 0 by -1)
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{
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req_rw = Mux(io.requestor(i).req_val, io.requestor(i).req_rw, req_rw)
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req_addr = Mux(io.requestor(i).req_val, io.requestor(i).req_addr, req_addr)
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req_wdata = Mux(io.requestor(i).req_val, io.requestor(i).req_wdata, req_wdata)
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req_tag = Mux(io.requestor(i).req_val, Cat(io.requestor(i).req_tag, UFix(i, log2up(n))), req_tag)
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}
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// Set read/write bit. I$ always reads
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io.mem.req_rw :=
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Mux(io.dcache.req_val, io.dcache.req_rw,
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Mux(io.icache.req_val, Bool(false),
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Mux(io.vicache.req_val, Bool(false),
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io.htif.req_rw)))
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io.mem.req_val := req_val
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io.mem.req_rw := req_rw
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io.mem.req_addr := req_addr
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io.mem.req_wdata := req_wdata
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io.mem.req_tag := req_tag
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// Give priority to D$
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io.mem.req_addr :=
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Mux(io.dcache.req_val, io.dcache.req_addr,
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Mux(io.icache.req_val, io.icache.req_addr,
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Mux(io.vicache.req_val, io.vicache.req_addr,
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io.htif.req_addr)))
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io.mem.req_wdata := Mux(io.dcache.req_val, io.dcache.req_wdata, io.htif.req_wdata)
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// low bit of tag to indicate D$, I$, and VI$
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val t_dcache :: t_icache :: t_vicache :: t_htif :: Nil = Enum(4){ UFix() }
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io.mem.req_tag :=
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Mux(io.dcache.req_val, Cat(io.dcache.req_tag, t_dcache),
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Mux(io.icache.req_val, Cat(io.icache.req_tag, t_icache),
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Mux(io.vicache.req_val, t_vicache,
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t_htif)))
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// *****************************
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// Interface to caches
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// *****************************
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// Read for request from cache if the memory is ready. Give priority to D$.
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// This way, writebacks will never be interrupted by I$ refills.
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io.dcache.req_rdy := io.mem.req_rdy;
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io.icache.req_rdy := io.mem.req_rdy && !io.dcache.req_val;
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io.vicache.req_rdy := io.mem.req_rdy && !io.dcache.req_val && !io.icache.req_val
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io.htif.req_rdy := io.mem.req_rdy && !io.dcache.req_val && !io.icache.req_val && !io.vicache.req_val
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// Response will only be valid for D$ or I$ not both because of tag bits
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io.dcache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_dcache)
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io.icache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_icache)
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io.vicache.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_vicache)
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io.htif.resp_val := io.mem.resp_val && (io.mem.resp_tag(1,0) === t_htif)
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// Feed through data to both
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io.dcache.resp_data := io.mem.resp_data;
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io.icache.resp_data := io.mem.resp_data;
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io.vicache.resp_data := io.mem.resp_data
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io.htif.resp_data := io.mem.resp_data
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io.dcache.resp_tag := io.mem.resp_tag >> UFix(2)
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io.icache.resp_tag := io.mem.resp_tag >> UFix(2)
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for (i <- 0 until n)
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{
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io.requestor(i).resp_val := io.mem.resp_val && io.mem.resp_tag(log2up(n)-1,0) === UFix(i)
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io.requestor(i).resp_data := io.mem.resp_data
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io.requestor(i).resp_tag := io.mem.resp_tag >> UFix(log2up(n))
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}
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}
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}
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@ -17,20 +17,10 @@ class ioImem(view: List[String] = null) extends Bundle (view)
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val resp_val = Bool(OUTPUT);
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}
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// interface between I$ and memory (128 bits wide)
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class ioICache(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
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val resp_val = Bool(OUTPUT);
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}
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class ioRocketICache extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioICache().flip();
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val mem = new ioDCache().flip()
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}
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// basic direct mapped instruction cache
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@ -139,6 +129,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
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io.cpu.resp_data := data_mux.io.out
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io.mem.req_val := (state === s_request);
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io.mem.req_rw := Bool(false)
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io.mem.req_addr := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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// control state machine
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@ -5,20 +5,9 @@ import Node._;
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import Constants._;
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import scala.math._;
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class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(PADDR_BITS - OFFSET_BITS, OUTPUT);
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val req_val = Bool(OUTPUT);
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val req_rdy = Bool(INPUT);
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val req_tag = Bits(IMEM_TAG_BITS, OUTPUT);
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val resp_data = Bits(MEM_DATA_BITS, INPUT);
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val resp_val = Bool(INPUT);
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val resp_tag = Bits(IMEM_TAG_BITS, INPUT);
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}
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class ioIPrefetcher extends Bundle() {
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val icache = new ioICache();
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val mem = new ioIPrefetcherMem();
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val icache = new ioDCache();
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val mem = new ioDCache().flip()
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val invalidate = Bool(INPUT)
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}
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@ -41,7 +30,8 @@ class rocketIPrefetcher extends Component() {
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val ip_mem_resp_val = io.mem.resp_val && io.mem.resp_tag(0).toBool;
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io.mem.req_val := io.icache.req_val & ~hit | (state === s_req_wait);
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io.mem.req_tag := !(io.icache.req_val && !hit);
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io.mem.req_rw := Bool(false)
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io.mem.req_tag := Mux(io.icache.req_val && !hit, UFix(0), UFix(1))
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io.mem.req_addr := Mux(io.mem.req_tag(0).toBool, prefetch_addr, io.icache.req_addr);
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val fill_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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@ -21,13 +21,13 @@ class Top() extends Component {
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val icache_pf = new rocketIPrefetcher();
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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val dcache = new HellaCacheUniproc();
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val arbiter = new rocketMemArbiter();
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arbiter.io.mem <> io.mem;
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arbiter.io.dcache <> dcache.io.mem;
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arbiter.io.icache <> icache_pf.io.mem;
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arbiter.io.vicache <> vicache.io.mem
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arbiter.io.htif <> htif.io.mem
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val arbiter = new rocketMemArbiter(4);
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arbiter.io.requestor(0) <> dcache.io.mem
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arbiter.io.requestor(1) <> icache_pf.io.mem
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arbiter.io.requestor(2) <> vicache.io.mem
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arbiter.io.requestor(3) <> htif.io.mem
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arbiter.io.mem <> io.mem
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htif.io.host <> io.host
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cpu.io.host <> htif.io.cpu(0);
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