commit
612f96b2af
@ -29,10 +29,10 @@ case object BroadcastConfig extends Field[BroadcastConfig]
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case class BankedL2Config(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: (Int, Parameters) => (TLInwardNode, TLOutwardNode) = { case (lineBytes, p) =>
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coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case p =>
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val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
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val bh = LazyModule(new TLBroadcast(lineBytes, nTrackers, bufferless))
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(bh.node, bh.node)
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val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
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(bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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@ -130,7 +130,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
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output := bankBar.node
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val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
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for (i <- 0 until l2Config.nBanksPerChannel) {
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val (in, out) = l2Config.coherenceManager(l1tol2_lineBytes, p)
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val (in, out) = l2Config.coherenceManager(p)
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in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
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bankBar.node := out
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}
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@ -12,32 +12,59 @@ import rocket._
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/////
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trait L2MasterPort extends CoreplexNetwork
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{
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val module: L2MasterPortModule
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val l2in = TLInputNode()
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l1tol2.node := l2in
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}
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trait L2MasterPortBundle extends CoreplexNetworkBundle
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{
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val outer: L2MasterPort
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val l2in = outer.l2in.bundleIn
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}
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trait L2MasterPortModule extends CoreplexNetworkModule
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{
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val outer: L2MasterPort
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val io: L2MasterPortBundle
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}
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/////
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class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
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with CoreplexRISCVPlatform
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with RocketPlex {
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with L2MasterPort
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with RocketTiles {
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override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
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}
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class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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with CoreplexRISCVPlatformBundle
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with RocketPlexBundle
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with L2MasterPortBundle
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with RocketTilesBundle
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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with CoreplexRISCVPlatformModule
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with RocketPlexModule
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with L2MasterPortModule
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with RocketTilesModule
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/////
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class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
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with CoreplexRISCVPlatform
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with AsyncRocketPlex {
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with L2MasterPort
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with AsyncRocketTiles {
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override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
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}
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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with CoreplexRISCVPlatformBundle
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with AsyncRocketPlexBundle
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with L2MasterPortBundle
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with AsyncRocketTilesBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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with CoreplexRISCVPlatformModule
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with AsyncRocketPlexModule
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with L2MasterPortModule
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with AsyncRocketTilesModule
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@ -8,8 +8,8 @@ import uncore.coherence._
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import rocket._
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import uncore.devices.NTiles
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trait RocketPlex extends CoreplexRISCVPlatform {
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val module: RocketPlexModule
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trait RocketTiles extends CoreplexRISCVPlatform {
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val module: RocketTilesModule
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val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) }
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val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
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@ -22,13 +22,13 @@ trait RocketPlex extends CoreplexRISCVPlatform {
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}
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}
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trait RocketPlexBundle extends CoreplexRISCVPlatformBundle {
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val outer: CoreplexRISCVPlatform
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trait RocketTilesBundle extends CoreplexRISCVPlatformBundle {
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val outer: RocketTiles
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}
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trait RocketPlexModule extends CoreplexRISCVPlatformModule {
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val outer: RocketPlex
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val io: RocketPlexBundle
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trait RocketTilesModule extends CoreplexRISCVPlatformModule {
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val outer: RocketTiles
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val io: RocketTilesBundle
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outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
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tile.io.hartid := UInt(i)
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@ -67,8 +67,8 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
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}
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}
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trait AsyncRocketPlex extends CoreplexRISCVPlatform {
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val module: AsyncRocketPlexModule
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trait AsyncRocketTiles extends CoreplexRISCVPlatform {
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val module: AsyncRocketTilesModule
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val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) }
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val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
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@ -81,8 +81,8 @@ trait AsyncRocketPlex extends CoreplexRISCVPlatform {
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}
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}
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trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle {
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val outer: CoreplexRISCVPlatform
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trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle {
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val outer: AsyncRocketTiles
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val tcrs = Vec(nTiles, new Bundle {
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val clock = Clock(INPUT)
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@ -90,9 +90,9 @@ trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle {
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})
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}
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trait AsyncRocketPlexModule extends CoreplexRISCVPlatformModule {
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val outer: AsyncRocketPlex
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val io: AsyncRocketPlexBundle
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trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule {
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val outer: AsyncRocketTiles
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val io: AsyncRocketTilesBundle
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outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
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tile.clock := io.tcrs(i).clock
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@ -12,14 +12,14 @@ class TestHarness(q: Parameters) extends Module {
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}
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implicit val p = q
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val dut = Module(LazyModule(new GroundTestTop(new GroundTestCoreplex()(_))).module)
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val dut = Module(LazyModule(new GroundTestTop).module)
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io.success := dut.io.success
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if (dut.io.mem_axi4.nonEmpty) {
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val memSize = p(ExtMem).size
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require(memSize % dut.io.mem_axi4.size == 0)
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for (axi <- dut.io.mem_axi4) {
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Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
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for (axi4 <- dut.io.mem_axi4) {
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Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4
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}
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}
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}
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@ -6,20 +6,25 @@ import diplomacy._
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import coreplex._
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import rocketchip._
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class GroundTestTop[+C <: GroundTestCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
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with DirectConnection
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class GroundTestTop(implicit p: Parameters) extends BaseTop
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with PeripheryMasterAXI4Mem
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with PeripheryTestRAM {
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override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this))
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val coreplex = LazyModule(new GroundTestCoreplex)
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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(mem zip coreplex.mem) foreach { case (m, c) => m := c }
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}
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class GroundTestTopBundle[+L <: GroundTestTop[GroundTestCoreplex]](_outer: L) extends BaseTopBundle(_outer)
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class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryMasterAXI4MemBundle
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with PeripheryTestRAMBundle {
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val success = Bool(OUTPUT)
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}
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class GroundTestTopModule[+L <: GroundTestTop[GroundTestCoreplex], +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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class GroundTestTopModule[+L <: GroundTestTop, +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with PeripheryMasterAXI4MemModule
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with PeripheryTestRAMModule {
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io.success := outer.coreplex.module.io.success
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@ -11,21 +11,19 @@ import uncore.tilelink2._
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import uncore.devices._
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import util._
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import rocket._
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import coreplex._
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/** Enable or disable monitoring of Diplomatic buses */
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case object TLEmitMonitors extends Field[Boolean]
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abstract class BareTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit val p: Parameters) extends LazyModule {
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val coreplex = LazyModule(_coreplex(p))
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abstract class BareTop(implicit val p: Parameters) extends LazyModule {
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TopModule.contents = Some(this)
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}
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abstract class BareTopBundle[+L <: BareTop[BaseCoreplex]](_outer: L) extends Bundle {
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abstract class BareTopBundle[+L <: BareTop](_outer: L) extends Bundle {
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val outer = _outer
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}
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abstract class BareTopModule[+L <: BareTop[BaseCoreplex], +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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@ -45,8 +43,6 @@ trait TopNetwork extends HasPeripheryParameters {
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TLWidthWidget(socBusConfig.beatBytes)(
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TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
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socBus.node))
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var coreplexMem = Seq[TLOutwardNode]()
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}
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trait TopNetworkBundle extends HasPeripheryParameters {
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@ -61,22 +57,23 @@ trait TopNetworkModule extends HasPeripheryParameters {
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}
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/** Base Top with no Periphery */
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class BaseTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BareTop(_coreplex)
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class BaseTop(implicit p: Parameters) extends BareTop
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with TopNetwork {
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override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
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}
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class BaseTopBundle[+L <: BaseTop[BaseCoreplex]](_outer: L) extends BareTopBundle(_outer)
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class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
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with TopNetworkBundle
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class BaseTopModule[+L <: BaseTop[BaseCoreplex], +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with TopNetworkModule
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trait DirectConnection extends TopNetwork {
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val coreplex: BaseCoreplex
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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coreplexMem = coreplex.mem
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trait L2Crossbar extends TopNetwork {
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val l2 = LazyModule(new TLXbar)
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}
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trait L2CrossbarBundle extends TopNetworkBundle {
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}
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trait L2CrossbarModule extends TopNetworkModule {
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}
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@ -5,56 +5,48 @@ package rocketchip
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import Chisel._
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import config._
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import junctions._
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import coreplex._
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import rocketchip._
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/** Example Top with Periphery */
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class ExampleTop[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
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with DirectConnection
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/** Example Top with Periphery (w/o coreplex) */
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abstract class ExampleTop(implicit p: Parameters) extends BaseTop
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with PeripheryExtInterrupts
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with PeripheryMasterAXI4Mem
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with PeripheryMasterAXI4MMIO {
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with PeripheryMasterAXI4MMIO
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with PeripherySlaveAXI4 {
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override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
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}
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class ExampleTopBundle[+L <: ExampleTop[BaseCoreplex]](_outer: L) extends BaseTopBundle(_outer)
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class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryExtInterruptsBundle
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with PeripheryMasterAXI4MemBundle
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with PeripheryMasterAXI4MMIOBundle
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with PeripherySlaveAXI4Bundle
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class ExampleTopModule[+L <: ExampleTop[BaseCoreplex], +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with PeripheryExtInterruptsModule
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with PeripheryMasterAXI4MemModule
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with PeripheryMasterAXI4MMIOModule
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with PeripherySlaveAXI4Module
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class ExampleRocketTop[+C <: DefaultCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
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class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
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with PeripheryBootROM
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with PeripheryDTM
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with PeripheryCounter
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with HardwiredResetVector {
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with HardwiredResetVector
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with RocketPlexMaster {
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override lazy val module = new ExampleRocketTopModule(this, () => new ExampleRocketTopBundle(this))
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}
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class ExampleRocketTopBundle[+L <: ExampleRocketTop[DefaultCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
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class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
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with PeripheryBootROMBundle
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with PeripheryDTMBundle
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with PeripheryCounterBundle
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with HardwiredResetVectorBundle
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with RocketPlexMasterBundle
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class ExampleRocketTopModule[+L <: ExampleRocketTop[DefaultCoreplex], +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
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class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
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with PeripheryBootROMModule
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with PeripheryDTMModule
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with PeripheryCounterModule
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with HardwiredResetVectorModule
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/** Example Top with TestRAM */
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class ExampleTopWithTestRAM[+C <: BaseCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends ExampleTop(_coreplex)
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with PeripheryTestRAM {
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override lazy val module = new ExampleTopWithTestRAMModule(this, () => new ExampleTopWithTestRAMBundle(this))
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}
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class ExampleTopWithTestRAMBundle[+L <: ExampleTopWithTestRAM[BaseCoreplex]](_outer: L) extends ExampleTopBundle(_outer)
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with PeripheryTestRAMBundle
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class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM[BaseCoreplex], +B <: ExampleTopWithTestRAMBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
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with PeripheryTestRAMModule
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with RocketPlexMasterModule
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@ -71,16 +71,17 @@ trait PeripheryExtInterruptsModule {
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/////
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trait PeripheryMasterAXI4Mem {
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this: BaseTop[BaseCoreplex] with TopNetwork =>
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this: TopNetwork =>
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val module: PeripheryMasterAXI4MemModule
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private val config = p(ExtMem)
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private val channels = coreplexMem.size
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private val channels = p(BankedL2Config).nMemoryChannels
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val mem_axi4 = coreplexMem.zipWithIndex.map { case (node, i) =>
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val mem_axi4 = Seq.tabulate(channels) { i =>
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val c_size = config.size/channels
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val c_base = config.base + c_size*i
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val axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
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AXI4BlindOutputNode(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(c_base, c_size-1)),
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regionType = RegionType.UNCACHED, // cacheable
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@ -89,14 +90,12 @@ trait PeripheryMasterAXI4Mem {
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supportsRead = TransferSizes(1, 256),
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interleavedId = Some(0))), // slave does not interleave read responses
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beatBytes = config.beatBytes))
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}
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axi4 :=
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// AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff
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TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
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TLWidthWidget(coreplex.l1tol2_beatBytes)( // convert width before attaching to the l1tol2
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node))
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axi4
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val mem = mem_axi4.map { node =>
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val foo = LazyModule(new TLToAXI4(config.idBits))
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node := foo.node
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foo.node
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}
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}
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@ -141,7 +140,7 @@ trait PeripheryMasterAXI4MMIOBundle {
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this: TopNetworkBundle {
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val outer: PeripheryMasterAXI4MMIO
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} =>
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val mmio_axi = outer.mmio_axi4.bundleOut
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val mmio_axi4 = outer.mmio_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MMIOModule {
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@ -154,6 +153,31 @@ trait PeripheryMasterAXI4MMIOModule {
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/////
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// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
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trait PeripherySlaveAXI4 extends L2Crossbar {
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private val axiIdBits = 8
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private val tlIdBits = 2 // at most 4 AXI requets inflight at a time
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val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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id = IdRange(0, 1 << axiIdBits)))))
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l2.node := TLSourceShrinker(1 << tlIdBits)(AXI4ToTL()(AXI4Fragmenter()(l2_axi4)))
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}
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trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {
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val outer: PeripherySlaveAXI4
|
||||
val l2_axi4 = outer.l2_axi4.bundleIn
|
||||
}
|
||||
|
||||
trait PeripherySlaveAXI4Module extends L2CrossbarModule {
|
||||
val outer: PeripherySlaveAXI4
|
||||
val io: PeripherySlaveAXI4Bundle
|
||||
// nothing to do
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryBootROM {
|
||||
this: TopNetwork =>
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
|
32
src/main/scala/rocketchip/RocketPlexMaster.scala
Normal file
32
src/main/scala/rocketchip/RocketPlexMaster.scala
Normal file
@ -0,0 +1,32 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package rocketchip
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import uncore.tilelink2._
|
||||
import uncore.devices._
|
||||
import util._
|
||||
import coreplex._
|
||||
|
||||
trait RocketPlexMaster extends L2Crossbar {
|
||||
val module: RocketPlexMasterModule
|
||||
val mem: Seq[TLInwardNode]
|
||||
|
||||
val coreplex = LazyModule(new DefaultCoreplex)
|
||||
|
||||
coreplex.l2in := l2.node
|
||||
socBus.node := coreplex.mmio
|
||||
coreplex.mmioInt := intBus.intnode
|
||||
(mem zip coreplex.mem) foreach { case (m, c) => m := c }
|
||||
}
|
||||
|
||||
trait RocketPlexMasterBundle extends L2CrossbarBundle {
|
||||
val outer: RocketPlexMaster
|
||||
}
|
||||
|
||||
trait RocketPlexMasterModule extends L2CrossbarModule {
|
||||
val outer: RocketPlexMaster
|
||||
val io: RocketPlexMasterBundle
|
||||
}
|
@ -14,7 +14,7 @@ class TestHarness(q: Parameters) extends Module {
|
||||
val success = Bool(OUTPUT)
|
||||
}
|
||||
implicit val p = q
|
||||
val dut = Module(LazyModule(new ExampleRocketTop(new DefaultCoreplex()(_))).module)
|
||||
val dut = Module(LazyModule(new ExampleRocketTop).module)
|
||||
|
||||
for (int <- dut.io.interrupts(0))
|
||||
int := Bool(false)
|
||||
@ -22,15 +22,22 @@ class TestHarness(q: Parameters) extends Module {
|
||||
if (dut.io.mem_axi4.nonEmpty) {
|
||||
val memSize = p(ExtMem).size
|
||||
require(memSize % dut.io.mem_axi4.size == 0)
|
||||
for (axi <- dut.io.mem_axi4) {
|
||||
Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
|
||||
for (axi4 <- dut.io.mem_axi4) {
|
||||
Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4
|
||||
}
|
||||
}
|
||||
|
||||
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success)
|
||||
|
||||
val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module)
|
||||
mmio_sim.io.axi <> dut.io.mmio_axi
|
||||
mmio_sim.io.axi4 <> dut.io.mmio_axi4
|
||||
|
||||
val l2_axi4 = dut.io.l2_axi4(0)
|
||||
l2_axi4.ar.valid := Bool(false)
|
||||
l2_axi4.aw.valid := Bool(false)
|
||||
l2_axi4.w .valid := Bool(false)
|
||||
l2_axi4.r .ready := Bool(true)
|
||||
l2_axi4.b .ready := Bool(true)
|
||||
}
|
||||
|
||||
class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
|
||||
@ -42,7 +49,7 @@ class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule {
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val axi = node.bundleIn
|
||||
val axi4 = node.bundleIn
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -56,8 +56,8 @@ object GenerateConfigString {
|
||||
def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
|
||||
val c = CoreplexParameters()(p)
|
||||
val res = new StringBuilder
|
||||
res append plic.module.globalConfigString
|
||||
res append clint.module.globalConfigString
|
||||
res append plic.globalConfigString
|
||||
res append clint.globalConfigString
|
||||
res append "core {\n"
|
||||
for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
|
||||
val isa = {
|
||||
@ -71,8 +71,8 @@ object GenerateConfigString {
|
||||
res append s" $i {\n"
|
||||
res append " 0 {\n"
|
||||
res append s" isa $isa;\n"
|
||||
res append clint.module.hartConfigStrings(i)
|
||||
res append plic.module.hartConfigStrings(i)
|
||||
res append clint.hartConfigStrings(i)
|
||||
res append plic.hartConfigStrings(i)
|
||||
res append " };\n"
|
||||
res append " };\n"
|
||||
}
|
||||
|
@ -68,6 +68,43 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
|
||||
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(contextsPerHart))) },
|
||||
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
|
||||
|
||||
/* Negotiated sizes */
|
||||
def nDevices = intnode.edgesIn.map(_.source.num).sum
|
||||
def nPriorities = min(maxPriorities, nDevices)
|
||||
def nHarts = intnode.edgesOut.map(_.source.num).sum
|
||||
|
||||
def context(i: Int, mode: Char) = mode match {
|
||||
case 'M' => i * contextsPerHart
|
||||
case 'S' => require(supervisor); i * contextsPerHart + 1
|
||||
}
|
||||
def claimAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
|
||||
def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
|
||||
def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
|
||||
|
||||
// Create the global PLIC config string
|
||||
lazy val globalConfigString = Seq(
|
||||
s"plic {\n",
|
||||
s" priority 0x${address.toString(16)};\n",
|
||||
s" pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
|
||||
s" ndevs ${nDevices};\n",
|
||||
s"};\n").mkString
|
||||
|
||||
// Create the per-Hart config string
|
||||
lazy val hartConfigStrings = Seq.tabulate(intnode.edgesOut.size) { i => (Seq(
|
||||
s" plic {\n",
|
||||
s" m {\n",
|
||||
s" ie 0x${enableAddr(i, 'M').toString(16)};\n",
|
||||
s" thresh 0x${threshAddr(i, 'M').toString(16)};\n",
|
||||
s" claim 0x${claimAddr(i, 'M').toString(16)};\n",
|
||||
s" };\n") ++ (if (!supervisor) Seq() else Seq(
|
||||
s" s {\n",
|
||||
s" ie 0x${enableAddr(i, 'S').toString(16)};\n",
|
||||
s" thresh 0x${threshAddr(i, 'S').toString(16)};\n",
|
||||
s" claim 0x${claimAddr(i, 'S').toString(16)};\n",
|
||||
s" };\n")) ++ Seq(
|
||||
s" };\n")).mkString
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val tl_in = node.bundleIn
|
||||
@ -91,45 +128,12 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
|
||||
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
|
||||
}
|
||||
|
||||
val nDevices = interrupts.size
|
||||
val nPriorities = min(maxPriorities, nDevices)
|
||||
val nHarts = harts.size
|
||||
require (nDevices == interrupts.size)
|
||||
require (nHarts == harts.size)
|
||||
|
||||
require(nDevices <= PLICConsts.maxDevices)
|
||||
require(nHarts > 0 && nHarts <= PLICConsts.maxHarts)
|
||||
|
||||
def context(i: Int, mode: Char) = mode match {
|
||||
case 'M' => i * contextsPerHart
|
||||
case 'S' => require(supervisor); i * contextsPerHart + 1
|
||||
}
|
||||
def claimAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
|
||||
def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
|
||||
def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
|
||||
|
||||
// Create the global PLIC config string
|
||||
val globalConfigString = Seq(
|
||||
s"plic {\n",
|
||||
s" priority 0x${address.toString(16)};\n",
|
||||
s" pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
|
||||
s" ndevs ${nDevices};\n",
|
||||
s"};\n").mkString
|
||||
|
||||
// Create the per-Hart config string
|
||||
val hartConfigStrings = io.harts.zipWithIndex.map { case (_, i) => (Seq(
|
||||
s" plic {\n",
|
||||
s" m {\n",
|
||||
s" ie 0x${enableAddr(i, 'M').toString(16)};\n",
|
||||
s" thresh 0x${threshAddr(i, 'M').toString(16)};\n",
|
||||
s" claim 0x${claimAddr(i, 'M').toString(16)};\n",
|
||||
s" };\n") ++ (if (!supervisor) Seq() else Seq(
|
||||
s" s {\n",
|
||||
s" ie 0x${enableAddr(i, 'S').toString(16)};\n",
|
||||
s" thresh 0x${threshAddr(i, 'S').toString(16)};\n",
|
||||
s" claim 0x${claimAddr(i, 'S').toString(16)};\n",
|
||||
s" };\n")) ++ Seq(
|
||||
s" };\n")).mkString
|
||||
}
|
||||
|
||||
// For now, use LevelGateways for all TL2 interrupts
|
||||
val gateways = Vec(interrupts.map { case i =>
|
||||
val gateway = Module(new LevelGateway)
|
||||
|
@ -63,15 +63,6 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
|
||||
tile.mtip := time.asUInt >= timecmp(i).asUInt
|
||||
}
|
||||
|
||||
val globalConfigString = Seq(
|
||||
s"rtc {\n",
|
||||
s" addr 0x${(address.base + ClintConsts.timeOffset).toString(16)};\n",
|
||||
s"};\n").mkString
|
||||
val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
|
||||
s" timecmp 0x${(address.base + ClintConsts.timecmpOffset(i)).toString(16)};\n",
|
||||
s" ipi 0x${(address.base + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
|
||||
}
|
||||
|
||||
/* 0000 msip hart 0
|
||||
* 0004 msip hart 1
|
||||
* 4000 mtimecmp hart 0 lo
|
||||
@ -96,3 +87,13 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Par
|
||||
extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
|
||||
new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)(
|
||||
new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
|
||||
{
|
||||
val globalConfigString = Seq(
|
||||
s"rtc {\n",
|
||||
s" addr 0x${(address + ClintConsts.timeOffset).toString(16)};\n",
|
||||
s"};\n").mkString
|
||||
val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
|
||||
s" timecmp 0x${(address + ClintConsts.timecmpOffset(i)).toString(16)};\n",
|
||||
s" ipi 0x${(address + ClintConsts.msipOffset(i)).toString(16)};\n").mkString
|
||||
}
|
||||
}
|
||||
|
@ -19,7 +19,6 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
|
||||
managerFn = { case Seq(mp) =>
|
||||
mp.copy(
|
||||
endSinkId = numTrackers,
|
||||
minLatency = 1,
|
||||
managers = mp.managers.map { m =>
|
||||
// We are the last level manager
|
||||
require (m.regionType != RegionType.CACHED)
|
||||
|
@ -72,7 +72,6 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
|
||||
mem.write(memAddress, wdata, in.a.bits.mask.toBools)
|
||||
}
|
||||
val ren = in.a.fire() && read
|
||||
def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
|
||||
rdata := holdUnless(mem.read(memAddress, ren), RegNext(ren))
|
||||
|
||||
// Tie off unused channels
|
||||
|
86
src/main/scala/uncore/tilelink2/SourceShrinker.scala
Normal file
86
src/main/scala/uncore/tilelink2/SourceShrinker.scala
Normal file
@ -0,0 +1,86 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
class TLSourceShrinker(maxInFlight: Int) extends LazyModule
|
||||
{
|
||||
require (maxInFlight > 0)
|
||||
|
||||
private val client = TLClientParameters(sourceId = IdRange(0, maxInFlight))
|
||||
val node = TLAdapterNode(
|
||||
// We erase all client information since we crush the source Ids
|
||||
clientFn = { case _ => TLClientPortParameters(clients = Seq(client)) },
|
||||
managerFn = { case Seq(mp) => mp })
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = node.bundleIn
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
val edgeIn = node.edgesIn(0)
|
||||
val edgeOut = node.edgesOut(0)
|
||||
val in = io.in(0)
|
||||
val out = io.out(0)
|
||||
|
||||
// Acquires cannot pass this adapter; it makes Probes impossible
|
||||
require (!edgeIn.client.anySupportProbe ||
|
||||
!edgeOut.manager.anySupportAcquire)
|
||||
|
||||
out.b.ready := Bool(true)
|
||||
out.c.valid := Bool(false)
|
||||
out.e.valid := Bool(false)
|
||||
in.b.valid := Bool(false)
|
||||
in.c.ready := Bool(true)
|
||||
in.e.ready := Bool(true)
|
||||
|
||||
if (maxInFlight >= edgeIn.client.endSourceId) {
|
||||
out.a <> in.a
|
||||
in.d <> out.d
|
||||
} else {
|
||||
// State tracking
|
||||
val sourceIdMap = Mem(maxInFlight, in.a.bits.source)
|
||||
val allocated = RegInit(UInt(0, width = maxInFlight))
|
||||
val nextFreeOH = ~(leftOR(~allocated) << 1) & ~allocated
|
||||
val nextFree = OHToUInt(nextFreeOH)
|
||||
val full = allocated.andR()
|
||||
|
||||
val a_first = edgeIn.first(in.a)
|
||||
val d_last = edgeIn.last(in.d)
|
||||
|
||||
val block = a_first && full
|
||||
in.a.ready := out.a.ready && !block
|
||||
out.a.valid := in.a.valid && !block
|
||||
out.a.bits := in.a.bits
|
||||
out.a.bits.source := holdUnless(nextFree, a_first)
|
||||
|
||||
in.d <> out.d
|
||||
in.d.bits.source := sourceIdMap(out.d.bits.source)
|
||||
|
||||
when (a_first && in.a.fire()) {
|
||||
sourceIdMap(nextFree) := in.a.bits.source
|
||||
}
|
||||
|
||||
val alloc = a_first && in.a.fire()
|
||||
val free = d_last && in.d.fire()
|
||||
val alloc_id = Mux(alloc, nextFreeOH, UInt(0))
|
||||
val free_id = Mux(free, UIntToOH(out.d.bits.source), UInt(0))
|
||||
allocated := (allocated | alloc_id) & ~free_id
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
object TLSourceShrinker
|
||||
{
|
||||
// applied to the TL source node; y.node := TLSourceShrinker(n)(x.node)
|
||||
def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
|
||||
shrinker.node := x
|
||||
shrinker.node
|
||||
}
|
||||
}
|
@ -13,6 +13,7 @@ package object tilelink2
|
||||
def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
|
||||
def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))
|
||||
def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
|
||||
def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
|
||||
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
|
||||
// Fill 1s from low bits to high bits
|
||||
def leftOR(x: UInt) = {
|
||||
|
@ -35,22 +35,27 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
|
||||
val empty = RegInit(Vec.fill(params.ways) { Bool(true) })
|
||||
val head = Reg(Vec(params.ways, UInt(width = log2Up(params.positions))))
|
||||
val tail = Reg(Vec(params.ways, UInt(width = log2Up(params.positions))))
|
||||
val next = Reg(Vec(params.positions, UInt(width = log2Up(params.positions))))
|
||||
val data = Reg(Vec(params.positions, params.gen))
|
||||
val next = Mem(params.positions, UInt(width = log2Up(params.positions)))
|
||||
val data = Mem(params.positions, params.gen)
|
||||
// optimized away for synthesis; used to confirm invariant
|
||||
val guard = RegInit(Vec.fill(params.positions) { Bool(false) })
|
||||
val guard = RegInit(UInt(0, width = params.positions))
|
||||
|
||||
when (io.enq.fire()) {
|
||||
data(io.enq.bits.pos) := io.enq.bits.data
|
||||
// ensure the user never stores to the same position twice
|
||||
assert (!guard(io.enq.bits.pos))
|
||||
guard(io.enq.bits.pos) := Bool(true)
|
||||
|
||||
when (!empty(io.enq.bits.way)) {
|
||||
next(tail(io.enq.bits.way)) := io.enq.bits.pos
|
||||
}
|
||||
}
|
||||
val setGuard = io.enq.fire() << io.enq.bits.pos
|
||||
|
||||
val deq = Wire(io.deq)
|
||||
io.deq <> deq
|
||||
|
||||
val waySelect = UIntToOH(io.enq.bits.way, params.ways)
|
||||
var clrGuard = UInt(0)
|
||||
for (i <- 0 until params.ways) {
|
||||
val enq = io.enq.fire() && waySelect(i)
|
||||
val last = head(i) === tail(i)
|
||||
@ -59,8 +64,6 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
|
||||
tail(i) := io.enq.bits.pos
|
||||
when (empty(i)) {
|
||||
head(i) := io.enq.bits.pos
|
||||
} .otherwise {
|
||||
next(tail(i)) := io.enq.bits.pos
|
||||
}
|
||||
}
|
||||
|
||||
@ -76,13 +79,15 @@ class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T],
|
||||
|
||||
when (deq(i).fire()) {
|
||||
head(i) := Mux(last, io.enq.bits.pos, next(head(i)))
|
||||
guard(deq(i).bits.pos) := Bool(false)
|
||||
}
|
||||
clrGuard = clrGuard | (deq(i).fire() << deq(i).bits.pos)
|
||||
|
||||
when (enq =/= deq(i).fire()) {
|
||||
empty(i) := deq(i).fire() && last
|
||||
}
|
||||
}
|
||||
|
||||
guard := (guard | setGuard) & ~clrGuard
|
||||
}
|
||||
|
||||
object PositionalMultiQueue
|
||||
|
Loading…
Reference in New Issue
Block a user