diff --git a/chisel b/chisel
index a39c41ac..d7e91308 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit a39c41ac3352fec1ec35b3e97c643f7e2f3843be
+Subproject commit d7e913088f840cff42d56920ab323c9b5f399b6f
diff --git a/src/main/scala/Backends.scala b/src/main/scala/Backends.scala
index d7db7042..c6bd0d92 100644
--- a/src/main/scala/Backends.scala
+++ b/src/main/scala/Backends.scala
@@ -62,6 +62,7 @@ class RocketChipBackend extends VerilogBackend
     initMap += (c -> init)
   }
 
+  transforms += {c => collectNodesIntoComp}
   transforms += addTopLevelPin
   transforms += addMemPin
 }