riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

util: AsyncQueue detect power-down/reset of non-empty queue

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-06 22:41:27 -07:00
parent 75bb94017b
commit 609fd97a71
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/util/AsyncQueue.scala
View File

@ -58,6 +58,9 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
io.widx := widx_reg io.widx := widx_reg
io.mem := mem io.mem := mem
// It is a fatal error to reset half a Queue while it still has data
assert (reset_n || widx === ridx)
} }
class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module { class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
@ -96,6 +99,9 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val ridx_reg = AsyncResetReg(ridx) val ridx_reg = AsyncResetReg(ridx)
io.ridx := ridx_reg io.ridx := ridx_reg
// It is a fatal error to reset half a Queue while it still has data
assert (reset_n || widx === ridx)
} }
class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Crossing[T] { class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Crossing[T] {