riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip

Browse Source
This commit is contained in:
John Wright 2016-02-25 10:39:43 -08:00 committed by Palmer Dabbelt
parent ebffd69b8e
commit 6095e7361e
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
uncore/src/main/scala/scr.scala
View File

@ -102,8 +102,6 @@ class SCRFile(prefix: String, baseAddress: BigInt)(implicit p: Parameters) exten
val scr_rdata = Wire(Vec(io.scr.rdata.size, Bits(width=scrDataBits))) val scr_rdata = Wire(Vec(io.scr.rdata.size, Bits(width=scrDataBits)))
for (i <- 0 until scr_rdata.size) for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i) scr_rdata(i) := io.scr.rdata(i)
scr_rdata(0) := UInt(nCores); map.allocate(0, "N_CORES")
scr_rdata(1) := UInt(p(MMIOBase) >> 20); map.allocate(1, "MMIO_BASE")
val read_addr = Reg(init = UInt(0, scrAddrBits)) val read_addr = Reg(init = UInt(0, scrAddrBits))
val resp_valid = Reg(init = Bool(false)) val resp_valid = Reg(init = Bool(false))