riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: RegisterRouter Unit Test

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-12 21:41:36 -07:00
parent 7005422651
commit 606f19a17f
4 changed files with 97 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/uncore/tilelink2/Fuzzer.scala
View File

@ -179,13 +179,15 @@ class TLFuzzer(nOperations: Int, inFlight: Int = 32) extends LazyModule
class TLFuzzRAM extends LazyModule
{
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0, 0xfff)))
val ram = LazyModule(new TLRAM(AddressSet(0, 0x3ff)))
val gpio = LazyModule(new RRTest1(0x400))
val xbar = LazyModule(new TLXbar)
val fuzz = LazyModule(new TLFuzzer(1000))
val fuzz = LazyModule(new TLFuzzer(5000))
model.node := fuzz.node
xbar.node := TLWidthWidget(TLHintHandler(model.node), 16)
ram.node := TLFragmenter(TLBuffer(xbar.node), 4, 256)
gpio.node := TLFragmenter(TLBuffer(xbar.node), 4, 32)
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished