riscv/rocket-chip
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diplomacy: eliminate some wasted IdentityNodes using cross-module refs

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This commit is contained in:
Wesley W. Terpstra
2017-09-23 00:04:50 -07:00
parent bc225a4e82
commit 60614055e3
9 changed files with 64 additions and 87 deletions
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14
src/main/scala/rocket/ICache.scala
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@ -51,9 +51,9 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
val device = new SimpleDevice("itim", Seq("sifive,itim0"))
val slaveNode = icacheParams.itimAddr.map { itimAddr =>
val wordBytes = icacheParams.fetchBytes
TLManagerNode(Seq(TLManagerPortParameters(
private val wordBytes = icacheParams.fetchBytes
val slaveNode =
TLManagerNode(icacheParams.itimAddr.toSeq.map { itimAddr => TLManagerPortParameters(
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg("mem"),
@ -64,8 +64,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
supportsGet = TransferSizes(1, wordBytes),
fifoId = Some(0))), // requests handled in FIFO order
beatBytes = wordBytes,
minLatency = 1)))
}
minLatency = 1)})
}
class ICacheResp(outer: ICache) extends Bundle {
@ -110,9 +109,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val io = IO(new ICacheBundle(outer))
val (tl_out, edge_out) = outer.masterNode.out(0)
// Option.unzip does not exist :-(
// val (tl_in, edge_in) = outer.slaveNode.map(_.in(0)).unzip
val tl_in = outer.slaveNode.map(_.in(0)._1)
val edge_in = outer.slaveNode.map(_.in(0)._2)
val tl_in = outer.slaveNode.in.headOption.map(_._1)
val edge_in = outer.slaveNode.in.headOption.map(_._2)
val tECC = cacheParams.tagECC
val dECC = cacheParams.dataECC