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[debug]: fix issue with subword select logic

This commit is contained in:
Megan Wachs 2016-06-03 15:45:20 -07:00 committed by Andrew Waterman
parent 3e8322816b
commit 605fb5b92f

View File

@ -842,7 +842,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
val sbWrDataWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrData((ii+1)*32 - 1, ii*32)}
val sbWrMaskWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrMask ((ii+1)*32 -1, ii*32)}
val sbWrSelTop = log2Up(tlDataBits/8)
val sbWrSelTop = log2Up(tlDataBits/8) - 1
val sbWrSelBottom = 2
SETHALTNOTWrData := sbWrDataWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))
@ -853,12 +853,12 @@ class DebugModule ()(implicit val p:cde.Parameters)
sbRamRdEn := sbRdEn
}
SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop) &&
sbWrMaskWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom)).orR &&
SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop + 1) &&
(sbWrMaskWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))).orR &&
sbWrEn
CLEARDEBINTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop) === CLEARDEBINT(sbAddrWidth-1, sbWrSelTop) &&
sbWrMaskWords(CLEARDEBINT(sbWrSelTop, sbWrSelBottom)).orR &&
CLEARDEBINTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === CLEARDEBINT(sbAddrWidth-1, sbWrSelTop + 1) &&
(sbWrMaskWords(CLEARDEBINT(sbWrSelTop, sbWrSelBottom))).orR &&
sbWrEn
}