[debug]: fix issue with subword select logic
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@ -842,7 +842,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
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val sbWrDataWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrData((ii+1)*32 - 1, ii*32)}
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val sbWrDataWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrData((ii+1)*32 - 1, ii*32)}
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val sbWrMaskWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrMask ((ii+1)*32 -1, ii*32)}
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val sbWrMaskWords = Vec.tabulate (tlDataBits / 32) {ii => sbWrMask ((ii+1)*32 -1, ii*32)}
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val sbWrSelTop = log2Up(tlDataBits/8)
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val sbWrSelTop = log2Up(tlDataBits/8) - 1
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val sbWrSelBottom = 2
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val sbWrSelBottom = 2
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SETHALTNOTWrData := sbWrDataWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))
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SETHALTNOTWrData := sbWrDataWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))
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@ -853,12 +853,12 @@ class DebugModule ()(implicit val p:cde.Parameters)
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sbRamRdEn := sbRdEn
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sbRamRdEn := sbRdEn
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}
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}
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SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop) &&
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SETHALTNOTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === SETHALTNOT(sbAddrWidth-1, sbWrSelTop + 1) &&
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sbWrMaskWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom)).orR &&
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(sbWrMaskWords(SETHALTNOT(sbWrSelTop, sbWrSelBottom))).orR &&
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sbWrEn
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sbWrEn
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CLEARDEBINTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop) === CLEARDEBINT(sbAddrWidth-1, sbWrSelTop) &&
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CLEARDEBINTWrEn := sbAddr(sbAddrWidth - 1, sbWrSelTop + 1) === CLEARDEBINT(sbAddrWidth-1, sbWrSelTop + 1) &&
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sbWrMaskWords(CLEARDEBINT(sbWrSelTop, sbWrSelBottom)).orR &&
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(sbWrMaskWords(CLEARDEBINT(sbWrSelTop, sbWrSelBottom))).orR &&
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sbWrEn
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sbWrEn
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}
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}
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