From 603b8af2eb2832c85ef48e3616faadf77e55c1e5 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 7 Mar 2017 17:26:09 -0800
Subject: [PATCH] Don't canonicalize 32-bit FP results in the various pipelines

It's redundant with the new scheme, so just adds HW for no reason.
---
 src/main/scala/tile/FPU.scala | 39 ++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
index ca5e1950..db3001e7 100644
--- a/src/main/scala/tile/FPU.scala
+++ b/src/main/scala/tile/FPU.scala
@@ -383,19 +383,22 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
     l2s.io.signedIn := ~in.bits.typ(0)
     l2s.io.in := intValue
     l2s.io.roundingMode := in.bits.rm
-    mux.data := Cat(UInt((BigInt(1) << (fLen - 32)) - 1), l2s.io.out)
-    mux.exc := l2s.io.exceptionFlags
 
     fLen match {
       case 32 =>
+        mux.data := l2s.io.out
+        mux.exc := l2s.io.exceptionFlags
       case 64 =>
         val l2d = Module(new hardfloat.INToRecFN(xLen, dExpWidth, dSigWidth))
         l2d.io.signedIn := ~in.bits.typ(0)
         l2d.io.in := intValue
         l2d.io.roundingMode := in.bits.rm
+
+        mux.data := Cat(l2d.io.out >> l2s.io.out.getWidth, l2s.io.out)
+        mux.exc := l2s.io.exceptionFlags
         when (!in.bits.single) {
-            mux.data := Cat(UInt((BigInt(1) << (fLen - 64)) - 1), l2d.io.out)
-            mux.exc := l2d.io.exceptionFlags
+          mux.data := l2d.io.out
+          mux.exc := l2d.io.exceptionFlags
         }
       }
     }
@@ -442,20 +445,22 @@ class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
       mux.data := Mux(isNaNOut, cNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
     }
 
-    fLen match {
-      case 32 =>
-      case 64 =>
-        when (in.bits.cmd === FCMD_CVT_FF) {
-          when (in.bits.single) {
-            val d2s = Module(new hardfloat.RecFNToRecFN(dExpWidth, dSigWidth, sExpWidth, sSigWidth))
-            d2s.io.in := in.bits.in1
-            d2s.io.roundingMode := in.bits.rm
-          mux.data := Cat(UInt((BigInt(1) << (fLen - 32)) - 1), d2s.io.out)
+  fLen match {
+    case 32 =>
+    case 64 =>
+      when (in.bits.cmd === FCMD_CVT_FF) {
+        val d2s = Module(new hardfloat.RecFNToRecFN(dExpWidth, dSigWidth, sExpWidth, sSigWidth))
+        d2s.io.in := in.bits.in1
+        d2s.io.roundingMode := in.bits.rm
+
+        val s2d = Module(new hardfloat.RecFNToRecFN(sExpWidth, sSigWidth, dExpWidth, dSigWidth))
+        s2d.io.in := in.bits.in1
+        s2d.io.roundingMode := in.bits.rm
+
+        when (in.bits.single) {
+          mux.data := Cat(s2d.io.out >> d2s.io.out.getWidth, d2s.io.out)
           mux.exc := d2s.io.exceptionFlags
         }.otherwise {
-          val s2d = Module(new hardfloat.RecFNToRecFN(sExpWidth, sSigWidth, dExpWidth, dSigWidth))
-          s2d.io.in := in.bits.in1
-          s2d.io.roundingMode := in.bits.rm
           mux.data := s2d.io.out
           mux.exc := s2d.io.exceptionFlags
         }
@@ -494,7 +499,7 @@ class FPUFMAPipe(val latency: Int, expWidth: Int, sigWidth: Int)(implicit p: Par
   fma.io.c := in.in3
 
   val res = Wire(new FPResult)
-  res.data := Cat(UInt((BigInt(1) << (fLen - (expWidth + sigWidth))) - 1), fma.io.out)
+  res.data := fma.io.out
   res.exc := fma.io.exceptionFlags
   io.out := Pipe(valid, res, latency-1)
 }