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export TL interface for Mem/MMIO and fix TL width adapters

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This commit is contained in:
Howard Mao
2016-06-30 18:20:43 -07:00
parent 39ec927a3f
commit 600f2da38a
5 changed files with 76 additions and 25 deletions
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5
src/main/scala/TestConfigs.scala
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@ -26,7 +26,7 @@ class WithGroundTest extends Config(
site(GroundTestMaxXacts)),
maxClientsPerPort = 1,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = site(MIFDataBeats),
dataBeats = 8,
dataBits = site(CacheBlockBytes)*8)
case BuildTiles => {
val groundtest = if (site(XLen) == 64)
@ -228,3 +228,6 @@ class FancyMemtestConfig extends Config(
new WithNCores(2) ++
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
class MIF128BitComparatorConfig extends Config(
new WithMIFDataBits(128) ++ new ComparatorConfig)