correctly initialize with seed
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@ -21,6 +21,12 @@ module TestDriver;
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reg [1023:0] vcdfile = 0;
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reg [1023:0] vcdfile = 0;
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initial
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initial
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begin
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begin
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// do not delete the line below
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// $random function needs to be called with the seed once
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// to affect all the downstream $random functions within the
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// Chisel-generated Verilog code
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$fdisplay(stderr, "seed %0d, testing $random %0x", unsigned'($get_initial_random_seed), $random($get_initial_random_seed));
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$value$plusargs("max-cycles=%d", max_cycles);
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$value$plusargs("max-cycles=%d", max_cycles);
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verbose = $test$plusargs("verbose");
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verbose = $test$plusargs("verbose");
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`ifdef DEBUG
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`ifdef DEBUG
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