rocket: add dtim and itim refs to cpus
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@ -31,6 +31,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
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private def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
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private def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
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private def ofStr(x: String) = Seq(ResourceString(x))
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private def ofStr(x: String) = Seq(ResourceString(x))
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private def ofRef(x: Device) = Seq(ResourceReference(x.label))
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val cpuDevice = new Device {
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val cpuDevice = new Device {
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def describe(resources: ResourceBindings): Description = {
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def describe(resources: ResourceBindings): Description = {
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@ -47,6 +48,12 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
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"d-cache-sets" -> ofInt(d.nSets),
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"d-cache-sets" -> ofInt(d.nSets),
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"d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
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"d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
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val dtim = scratch.map(d => Map(
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"sifive,dtim" -> ofRef(d.device))).getOrElse(Map())
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val itim = if (!frontend.icache.slaveNode.isDefined) Map() else Map(
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"sifive,itim" -> ofRef(frontend.icache.device))
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val icache = rocketParams.icache.map(i => Map(
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val icache = rocketParams.icache.map(i => Map(
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"i-cache-block-size" -> ofInt(block),
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"i-cache-block-size" -> ofInt(block),
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"i-cache-sets" -> ofInt(i.nSets),
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"i-cache-sets" -> ofInt(i.nSets),
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@ -86,7 +93,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
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"status" -> ofStr("okay"),
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"status" -> ofStr("okay"),
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"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
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"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
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"riscv,isa" -> ofStr(isa))
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"riscv,isa" -> ofStr(isa))
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++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb)
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++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim)
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}
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}
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}
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}
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val intcDevice = new Device {
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val intcDevice = new Device {
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