riscv/rocket-chip
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make DCache s1_nack less conservative for pipelined MMIO requests

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Yunsup Lee 2017-03-21 09:03:50 -07:00 committed by Wesley W. Terpstra
parent 4c00066746
commit 5eae7e1da4
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -172,7 +172,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH)
val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_update_meta = s2_hit_state =/= s2_new_hit_state
io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR) io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && tl_out.a.ready && !uncachedInFlight.asUInt.andR)
when (s2_valid && (!s2_valid_hit || s2_update_meta)) { s1_nack := true } when (io.cpu.s2_nack || (s2_valid_hit && s2_update_meta)) { s1_nack := true }
// exceptions // exceptions
val s1_storegen = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes) val s1_storegen = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes)