From 5e88ead984e463c8b19408b300b7dbaed5ea86ed Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 28 Sep 2015 11:52:27 -0700 Subject: [PATCH] Add pseudo-ops to instructions.scala --- rocket/src/main/scala/instructions.scala | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index f007ebc4..b5ab974f 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -192,6 +192,26 @@ object Instructions { def CUSTOM3_RD = BitPat("b?????????????????100?????1111011") def CUSTOM3_RD_RS1 = BitPat("b?????????????????110?????1111011") def CUSTOM3_RD_RS1_RS2 = BitPat("b?????????????????111?????1111011") + def SLLI_RV32 = BitPat("b0000000??????????001?????0010011") + def SRLI_RV32 = BitPat("b0000000??????????101?????0010011") + def SRAI_RV32 = BitPat("b0100000??????????101?????0010011") + def FRFLAGS = BitPat("b00000000000100000010?????1110011") + def FSFLAGS = BitPat("b000000000001?????001?????1110011") + def FSFLAGSI = BitPat("b000000000001?????101?????1110011") + def FRRM = BitPat("b00000000001000000010?????1110011") + def FSRM = BitPat("b000000000010?????001?????1110011") + def FSRMI = BitPat("b000000000010?????101?????1110011") + def FSCSR = BitPat("b000000000011?????001?????1110011") + def FRCSR = BitPat("b00000000001100000010?????1110011") + def RDCYCLE = BitPat("b11000000000000000010?????1110011") + def RDTIME = BitPat("b11000000000100000010?????1110011") + def RDINSTRET = BitPat("b11000000001000000010?????1110011") + def RDCYCLEH = BitPat("b11001000000000000010?????1110011") + def RDTIMEH = BitPat("b11001000000100000010?????1110011") + def RDINSTRETH = BitPat("b11001000001000000010?????1110011") + def ECALL = BitPat("b00000000000000000000000001110011") + def EBREAK = BitPat("b00000000000100000000000001110011") + def ERET = BitPat("b00010000000000000000000001110011") } object Causes { val misaligned_fetch = 0x0