From 213c1a4c81a37e230010a25a5a5ce5432a07ff31 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 14 Nov 2015 16:43:15 -0800 Subject: [PATCH] fix fdiv/fsqrt control bug in fpu --- rocket/src/main/scala/fpu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 2bf12d96..74f11bbb 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -609,7 +609,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) { val divSqrt = Module(new hardfloat.DivSqrtRecF64) divSqrt_inReady := Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div) val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt - divSqrt.io.inValid := mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) + divSqrt.io.inValid := mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_in_flight divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := fpiu.io.as_double.in1 divSqrt.io.b := fpiu.io.as_double.in2