AsyncQueueSource: don't feed reset into normal logic!
There is no need to block writes to mem during reset. The Queue must be empty anyway.
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@ -44,7 +44,7 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
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val ready = widx =/= (ridx ^ UInt(depth | depth >> 1))
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val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
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when (io.enq.fire() && !reset) { mem(index) := io.enq.bits }
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when (io.enq.fire()) { mem(index) := io.enq.bits }
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val ready_reg = AsyncResetReg(ready, 0)
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io.enq.ready := ready_reg
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