riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

AsyncQueueSource: don't feed reset into normal logic!

Browse Source 
There is no need to block writes to mem during reset.
The Queue must be empty anyway.
This commit is contained in:
Wesley W. Terpstra
2016-10-06 20:42:51 -07:00
parent 2f6985efd3
commit 5e2609bdd2
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/util/AsyncQueue.scala
View File

@@ -44,7 +44,7 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
val ready = widx =/= (ridx ^ UInt(depth | depth >> 1)) val ready = widx =/= (ridx ^ UInt(depth | depth >> 1))
val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1)) val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
when (io.enq.fire() && !reset) { mem(index) := io.enq.bits } when (io.enq.fire()) { mem(index) := io.enq.bits }
val ready_reg = AsyncResetReg(ready, 0) val ready_reg = AsyncResetReg(ready, 0)
io.enq.ready := ready_reg io.enq.ready := ready_reg