riscv/rocket-chip
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Add L2 TLB miss counter

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Andrew Waterman
2017-07-25 11:59:53 -07:00
parent 3ced04b70a
commit 5df8f0d1ea
2 changed files with 9 additions and 1 deletions
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3
src/main/scala/rocket/RocketCore.scala
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@ -106,7 +106,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
("D$ miss", () => io.dmem.perf.acquire),
("D$ release", () => io.dmem.perf.release),
("ITLB miss", () => io.imem.perf.tlbMiss),
("DTLB miss", () => io.dmem.perf.tlbMiss)))))
("DTLB miss", () => io.dmem.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val decode_table = {
(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++: