riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Synchronizers: remove some newlines and unncessary gen's

Browse Source
This commit is contained in:
Megan Wachs 2017-09-05 15:16:08 -07:00
parent a3bc5f2e33
commit 5df23c5514
1 changed files with 4 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/main/scala/util/SynchronizingReg.scala
View File

@ -22,21 +22,17 @@ import Chisel._
*/ */
abstract class AbstractPipelineReg(w: Int = 1) extends Module { abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = new Bundle { val io = new Bundle {
val d = UInt(INPUT, width = w) val d = UInt(INPUT, width = w)
val q = UInt(OUTPUT, width = w) val q = UInt(OUTPUT, width = w)
} }
} }
object AbstractPipelineReg { object AbstractPipelineReg {
def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen) val chain = Module(gen)
name.foreach{ chain.suggestName(_) } name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt chain.io.d := in.asUInt
chain.io.q.asTypeOf(in) chain.io.q.asTypeOf(in)
} }
} }
@ -58,13 +54,11 @@ class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String
sink.io.en := Bool(true) sink.io.en := Bool(true)
} }
io.q := chain.head.io.q io.q := chain.head.io.q
} }
object AsyncResetShiftReg { object AsyncResetShiftReg {
def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T = def apply [T <: Chisel.Data](in: T, depth: Int = 1, init: Int = 0, name: Option[String] = None ): T =
AbstractPipelineReg(gen = {new AsyncResetShiftReg(in.getWidth, depth, init)}, in, name) AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
} }
// Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does // Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
@ -75,9 +69,8 @@ class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AsyncRes
} }
object AsyncResetSynchronizerShiftReg { object AsyncResetSynchronizerShiftReg {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractPipelineReg(gen = {new AsyncResetSynchronizerShiftReg(in.getWidth, sync)}, in, name) AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync), in, name)
} }
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
@ -96,11 +89,9 @@ class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineRe
sink := source sink := source
} }
io.q := syncv.head io.q := syncv.head
} }
object SynchronizerShiftReg { object SynchronizerShiftReg {
def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T =
AbstractPipelineReg(gen = { new SynchronizerShiftReg(in.getWidth, sync)}, in, name) AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
} }