From 5dc3da008e7b3c4f1e29ed8a6329d4596ad05f3f Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sat, 11 Jul 2015 13:36:14 -0700
Subject: [PATCH] Use Chisel3 SeqMem construct

---
 uncore/src/main/scala/cache.scala     | 21 ++++++++-------------
 uncore/src/main/scala/memserdes.scala | 17 +++++++----------
 2 files changed, 15 insertions(+), 23 deletions(-)

diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index 608fe5da..0f92eaa0 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -154,12 +154,12 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
   when (rst) { rst_cnt := rst_cnt+UInt(1) }
 
   val metabits = rstVal.getWidth
-  val tag_arr = Mem(UInt(width = metabits*nWays), nSets, seqRead = true)
+  val tag_arr = SeqMem(UInt(width = metabits*nWays), nSets)
   when (rst || io.write.valid) {
     tag_arr.write(waddr, Fill(nWays, wdata), FillInterleaved(metabits, wmask))
   }
 
-  val tags = tag_arr(RegEnable(io.read.bits.idx, io.read.valid))
+  val tags = tag_arr.read(io.read.bits.idx, io.read.valid)
   io.resp := io.resp.fromBits(tags)
   io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
   io.write.ready := !rst
@@ -317,21 +317,16 @@ class L2DataRWIO extends L2HellaCacheBundle with HasL2DataReadIO with HasL2DataW
 class L2DataArray(delay: Int) extends L2HellaCacheModule {
   val io = new L2DataRWIO().flip
 
-  val wmask = FillInterleaved(8, io.write.bits.wmask)
-  val reg_raddr = Reg(UInt())
-  val array = Mem(Bits(width=rowBits), nWays*nSets*refillCycles, seqRead = true)
-  val waddr = Cat(OHToUInt(io.write.bits.way_en), io.write.bits.addr_idx, io.write.bits.addr_beat)
+  val array = SeqMem(Bits(width=rowBits), nWays*nSets*refillCycles)
+  val ren = !io.write.valid && io.read.valid
   val raddr = Cat(OHToUInt(io.read.bits.way_en), io.read.bits.addr_idx, io.read.bits.addr_beat)
-
-  when (io.write.bits.way_en.orR && io.write.valid) {
-    array.write(waddr, io.write.bits.data, wmask)
-  }.elsewhen (io.read.bits.way_en.orR && io.read.valid) {
-    reg_raddr := raddr
-  }
+  val waddr = Cat(OHToUInt(io.write.bits.way_en), io.write.bits.addr_idx, io.write.bits.addr_beat)
+  val wmask = FillInterleaved(8, io.write.bits.wmask)
+  when (io.write.valid) { array.write(waddr, io.write.bits.data, wmask) }
 
   val r_req = Pipe(io.read.fire(), io.read.bits)
   io.resp := Pipe(r_req.valid, r_req.bits, delay)
-  io.resp.bits.data := Pipe(r_req.valid, array(reg_raddr), delay).bits
+  io.resp.bits.data := Pipe(r_req.valid, array.read(raddr, ren), delay).bits
   io.read.ready := !io.write.valid
   io.write.ready := Bool(true)
 }
diff --git a/uncore/src/main/scala/memserdes.scala b/uncore/src/main/scala/memserdes.scala
index a4944e1e..e124b2be 100644
--- a/uncore/src/main/scala/memserdes.scala
+++ b/uncore/src/main/scala/memserdes.scala
@@ -482,19 +482,16 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
   val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2)
   do_flow := empty && io.deq.ready
 
-  val ram = Mem(data, entries, seqRead = true)
-  val ram_addr = Reg(Bits())
-  val ram_out_valid = Reg(Bool())
-  ram_out_valid := Bool(false)
-  when (do_enq) { ram(enq_ptr) := io.enq.bits }
-  when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) {
-    ram_out_valid := Bool(true)
-    ram_addr := Mux(io.deq.valid, Mux(deq_done, UInt(0), deq_ptr + UInt(1)), deq_ptr)
-  }
+  val ram = SeqMem(data, entries)
+  when (do_enq) { ram.write(enq_ptr, io.enq.bits) }
+
+  val ren = io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)
+  val raddr = Mux(io.deq.valid, Mux(deq_done, UInt(0), deq_ptr + UInt(1)), deq_ptr)
+  val ram_out_valid = Reg(next = ren)
 
   io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
   io.enq.ready := !full
-  io.deq.bits := Mux(empty, io.enq.bits, ram(ram_addr))
+  io.deq.bits := Mux(empty, io.enq.bits, ram.read(raddr, ren))
 }
 
 class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module