diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala
index 6d5ea3b0..0e99a933 100644
--- a/src/main/scala/rocket/TLB.scala
+++ b/src/main/scala/rocket/TLB.scala
@@ -74,17 +74,18 @@ class TLB(implicit edge: TLEdgeOut, val p: Parameters) extends Module with HasTL
   val prot_w = fastCheck(_.supportsPutFull)
   val prot_x = fastCheck(_.executable)
   val cacheable = fastCheck(_.supportsAcquireB)
+  val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes)
   val allSizes = TransferSizes(1, cacheBlockBytes)
   val amoSizes = TransferSizes(1, xLen/8)
   edge.manager.managers.foreach { m =>
     require (m.minAlignment >= 4096, s"MemoryMap region ${m.name} must be page-aligned (is ${m.minAlignment})")
-    require (!m.supportsGet        || m.supportsGet       .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}")
-    require (!m.supportsPutFull    || m.supportsPutFull   .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
-    require (!m.supportsAcquireB   || m.supportsAcquireB  .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireB} AcquireB, but must support ${allSizes}")
-    require (!m.supportsAcquireT   || m.supportsAcquireT  .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireT} AcquireT, but must support ${allSizes}")
-    require (!m.supportsLogical    || m.supportsLogical   .contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
-    require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
-    require (m.supportsAcquireT || !m.supportsPutFull || !m.supportsAcquireB,  s"MemoryMap region ${m.name} supports PutFull and AcquireB but not AcquireT")
+    require (!m.supportsGet        || m.supportsGet       .contains(allSizes),  s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}")
+    require (!m.supportsPutFull    || m.supportsPutFull   .contains(allSizes),  s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
+    require (!m.supportsAcquireB   || m.supportsAcquireB  .contains(xferSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}")
+    require (!m.supportsAcquireT   || m.supportsAcquireT  .contains(xferSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}")
+    require (!m.supportsLogical    || m.supportsLogical   .contains(amoSizes),  s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
+    require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes),  s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
+    require (m.supportsAcquireT || !m.supportsPutFull || !m.supportsAcquireB,   s"MemoryMap region ${m.name} supports PutFull and AcquireB but not AcquireT")
   }
 
   val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))