riscv/rocket-chip
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[rocket] Automatically kill D$ access on address exceptions

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Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
This commit is contained in:
Andrew Waterman
2016-08-02 15:24:19 -07:00
parent b54db0ba23
commit 5d4f6383f2
3 changed files with 9 additions and 15 deletions
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11
rocket/src/main/scala/rocket.scala
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@ -411,9 +411,9 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
}
}
val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
(mem_reg_load && bpu.io.xcpt_ld, UInt(Causes.breakpoint)),
(mem_reg_store && bpu.io.xcpt_st, UInt(Causes.breakpoint)),
(mem_breakpoint, UInt(Causes.breakpoint)),
(mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
(mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
(mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
@ -617,9 +617,12 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
io.dmem.req.bits.typ := ex_ctrl.mem_type
io.dmem.req.bits.phys := Bool(false)
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.s1_kill := killm_common || mem_xcpt
io.dmem.s1_data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
io.dmem.invalidate_lr := wb_xcpt
io.dmem.s1_data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
io.dmem.s1_kill := killm_common || mem_breakpoint
when (mem_xcpt && !io.dmem.s1_kill) {
assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive
}
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR