riscv/rocket-chip
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Add option to make misa read-only

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This commit is contained in:
Andrew Waterman 2017-09-20 19:16:34 -07:00
parent 09468a272b
commit 5cfe070932
3 changed files with 4 additions and 1 deletions
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1
src/main/scala/rocket/CSR.scala
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@ -606,6 +606,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (decoded_addr(CSRs.misa)) { when (decoded_addr(CSRs.misa)) {
val mask = UInt(isaStringToMask(isaMaskString), xLen) val mask = UInt(isaStringToMask(isaMaskString), xLen)
val f = wdata('f' - 'a') val f = wdata('f' - 'a')
if (coreParams.misaWritable)
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
} }
when (decoded_addr(CSRs.mip)) { when (decoded_addr(CSRs.mip)) {

1
src/main/scala/rocket/RocketCore.scala
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@ -24,6 +24,7 @@ case class RocketCoreParams(
nPMPs: Int = 8, nPMPs: Int = 8,
nPerfCounters: Int = 0, nPerfCounters: Int = 0,
haveBasicCounters: Boolean = true, haveBasicCounters: Boolean = true,
misaWritable: Boolean = true,
nL2TLBEntries: Int = 0, nL2TLBEntries: Int = 0,
mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true, mtvecWritable: Boolean = true,

1
src/main/scala/tile/Core.scala
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@ -29,6 +29,7 @@ trait CoreParams {
val nBreakpoints: Int val nBreakpoints: Int
val nPerfCounters: Int val nPerfCounters: Int
val haveBasicCounters: Boolean val haveBasicCounters: Boolean
val misaWritable: Boolean
val nL2TLBEntries: Int val nL2TLBEntries: Int
val mtvecInit: Option[BigInt] val mtvecInit: Option[BigInt]
val mtvecWritable: Boolean val mtvecWritable: Boolean