riscv/rocket-chip
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Add option to make misa read-only

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This commit is contained in:
Andrew Waterman
2017-09-20 19:16:34 -07:00
parent 09468a272b
commit 5cfe070932
3 changed files with 4 additions and 1 deletions
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3
src/main/scala/rocket/CSR.scala
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@ -606,7 +606,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (decoded_addr(CSRs.misa)) {
val mask = UInt(isaStringToMask(isaMaskString), xLen)
val f = wdata('f' - 'a')
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
if (coreParams.misaWritable)
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
}
when (decoded_addr(CSRs.mip)) {
// MIP should be modified based on the value in reg_mip, not the value