Merge pull request #1077 from freechipsproject/node-style
diplomacy: switch adapter methods to node style
This commit is contained in:
commit
5ca04a5c41
@ -25,8 +25,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
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val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
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val gpio = LazyModule(new RRTest0(0x100))
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model.node := fuzz.node
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xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node))
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xbar.node := TLToAHB(aFlow) := TLDelayer(0.1) := model.node := fuzz.node
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ram.node := xbar.node
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gpio.node := xbar.node
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@ -46,13 +45,13 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
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val fuzz = LazyModule(new TLFuzzer(txns))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
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model.node := fuzz.node
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node :=
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TLToAHB(aFlow)(
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TLDelayer(0.2)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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(node
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:= TLToAHB(aFlow)
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:= TLDelayer(0.2)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.2)
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:= model.node
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:= fuzz.node)
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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@ -68,13 +67,13 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
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val node = AHBIdentityNode()
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val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.2)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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AHBToTL()(
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node)))))
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(ram.node
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:= TLFragmenter(4, 16)
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:= TLDelayer(0.2)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.2)
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:= AHBToTL()
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:= node)
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lazy val module = new LazyModuleImp(this) { }
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}
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@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.ahb
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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@ -132,9 +131,5 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
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object AHBToTL
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{
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def apply()(x: AHBOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val tl = LazyModule(new AHBToTL)
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tl.node :=? x
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tl.node
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}
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def apply()(implicit p: Parameters) = LazyModule(new AHBToTL).node
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}
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@ -3,9 +3,11 @@
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package freechips.rocketchip.amba
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import Chisel._
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import freechips.rocketchip.diplomacy.OutwardNodeHandle
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import freechips.rocketchip.diplomacy._
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package object ahb
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{
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type AHBOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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type AHBInwardNode = InwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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type AHBNode = SimpleNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
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}
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@ -24,15 +24,15 @@ class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
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val ram = LazyModule(new APBRAM(AddressSet(0x0, 0xff)))
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val gpio = LazyModule(new RRTest0(0x100))
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model.node := fuzz.node
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ram.node := xbar.node
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gpio.node := xbar.node
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xbar.node :=
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TLToAPB(aFlow)(
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TLDelayer(0.2)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.2)(
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model.node))))
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(xbar.node
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:= TLToAPB(aFlow)
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:= TLDelayer(0.2)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.2)
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:= model.node
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:= fuzz.node)
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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@ -3,9 +3,11 @@
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package freechips.rocketchip.amba
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import Chisel._
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import freechips.rocketchip.diplomacy.OutwardNodeHandle
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import freechips.rocketchip.diplomacy._
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package object apb
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{
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type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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type APBInwardNode = InwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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type APBNode = SimpleNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
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}
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@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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@ -44,22 +43,12 @@ class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameter
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object AXI4AsyncCrossingSource
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{
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// applied to the AXI4 source node; y.node := AXI4AsyncCrossingSource()(x.node)
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def apply(sync: Int = 3)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4AsyncOutwardNode = {
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val source = LazyModule(new AXI4AsyncCrossingSource(sync))
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source.node :=? x
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source.node
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}
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def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSource(sync)).node
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}
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object AXI4AsyncCrossingSink
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{
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// applied to the AXI4 source node; y.node := AXI4AsyncCrossingSink()(x.node)
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def apply(depth: Int = 8, sync: Int = 3)(x: AXI4AsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
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sink.node :=? x
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sink.node
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}
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def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSink(depth, sync)).node
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}
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@deprecated("AXI4AsyncCrossing is fragile. Use AXI4AsyncCrossingSource and AXI4AsyncCrossingSink", "rocket-chip 1.2")
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@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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@ -46,18 +45,13 @@ class AXI4Buffer(
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object AXI4Buffer
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{
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// applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
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def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(BufferParams.default)(x)
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def apply(z: BufferParams) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(z, z)(x)
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def apply(aw: BufferParams, br: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br)(x)
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def apply() (implicit p: Parameters): AXI4Node = apply(BufferParams.default)
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def apply(z: BufferParams) (implicit p: Parameters): AXI4Node = apply(z, z)
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def apply(aw: BufferParams, br: BufferParams)(implicit p: Parameters): AXI4Node = apply(aw, aw, br, aw, br)
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def apply(
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aw: BufferParams,
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w: BufferParams,
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b: BufferParams,
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ar: BufferParams,
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r: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
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buffer.node :=? x
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buffer.node
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}
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r: BufferParams)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Buffer(aw, w, b, ar, r)).node
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}
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@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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@ -100,10 +99,5 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
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object AXI4Deinterleaver
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{
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// applied to the AXI4 source node; y.node := AXI4Deinterleaver()(x.node)
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def apply(maxReadBytes: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val deinterleaver = LazyModule(new AXI4Deinterleaver(maxReadBytes))
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deinterleaver.node :=? x
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deinterleaver.node
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}
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def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Deinterleaver(maxReadBytes)).node
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}
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@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.util.IrrevocableIO
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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@ -200,10 +199,5 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
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object AXI4Fragmenter
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{
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// applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
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def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val fragmenter = LazyModule(new AXI4Fragmenter)
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fragmenter.node :=? x
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fragmenter.node
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}
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def apply()(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Fragmenter).node
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}
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@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import scala.math.{min,max}
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@ -76,10 +75,5 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
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object AXI4IdIndexer
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{
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// applied to the AXI4 source node; y.node := AXI4IdIndexer(idBits)(x.node)
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def apply(idBits: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val indexer = LazyModule(new AXI4IdIndexer(idBits))
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indexer.node :=? x
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indexer.node
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}
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def apply(idBits: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4IdIndexer(idBits)).node
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}
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@ -25,10 +25,9 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
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val gpio = LazyModule(new RRTest1(0x400))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(true )(TLFragmenter(4, 16)(xbar.node))))
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gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(false)(TLFragmenter(4, 16)(xbar.node))))
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xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node
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ram.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(true ) := TLFragmenter(4, 16) := xbar.node
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gpio.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(false) := TLFragmenter(4, 16) := xbar.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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@ -48,10 +47,9 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
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val gpio = LazyModule(new RRTest0(0x400))
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(false)(xbar.node)))
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gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(true )(xbar.node)))
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xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node
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ram.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(false) := xbar.node
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gpio.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(true ) := xbar.node
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lazy val module = new LazyModuleImp(this) with UnitTestModule {
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io.finished := fuzz.module.io.finished
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@ -73,15 +71,15 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with
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val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
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val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
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model.node := fuzz.node
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node :=
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AXI4UserYanker()(
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AXI4Deinterleaver(64)(
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TLToAXI4()(
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TLDelayer(0.1)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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model.node))))))
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(node
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:= AXI4UserYanker()
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:= AXI4Deinterleaver(64)
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:= TLToAXI4()
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:= TLDelayer(0.1)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.1)
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:= model.node
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:= fuzz.node)
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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@ -99,19 +97,19 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
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val ram = LazyModule(new TLRAM(fuzzAddr))
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val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
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ram.node := TLFragmenter(4, 16)(xbar.node)
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ram.node := TLFragmenter(4, 16) := xbar.node
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error.node := xbar.node
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xbar.node :=
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TLFIFOFixer()(
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TLDelayer(0.1)(
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TLBuffer(BufferParams.flow)(
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TLDelayer(0.1)(
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AXI4ToTL()(
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AXI4UserYanker(Some(4))(
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AXI4Fragmenter()(
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AXI4IdIndexer(2)(
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node))))))))
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(xbar.node
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:= TLFIFOFixer()
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:= TLDelayer(0.1)
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:= TLBuffer(BufferParams.flow)
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:= TLDelayer(0.1)
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:= AXI4ToTL()
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:= AXI4UserYanker(Some(4))
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:= AXI4Fragmenter()
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:= AXI4IdIndexer(2)
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:= node)
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lazy val module = new LazyModuleImp(this) { }
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}
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|
@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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@ -161,9 +160,5 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
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object AXI4ToTL
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{
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def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val tl = LazyModule(new AXI4ToTL)
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tl.node :=? x
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tl.node
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}
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def apply()(implicit p: Parameters) = LazyModule(new AXI4ToTL).node
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}
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|
@ -3,7 +3,6 @@
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.UIntToOH1
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@ -92,10 +91,5 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
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object AXI4UserYanker
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{
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// applied to the AXI4 source node; y.node := AXI4UserYanker(idBits, maxFlight)(x.node)
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def apply(capMaxFlight: Option[Int] = None)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val yanker = LazyModule(new AXI4UserYanker(capMaxFlight))
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yanker.node :=? x
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yanker.node
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}
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def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4UserYanker(capMaxFlight)).node
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}
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|
@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
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package object axi4
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{
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type AXI4Node = SimpleNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
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type AXI4AsyncOutwardNode = OutwardNodeHandle[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]
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type AXI4Node = NodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle, AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
|
||||
type AXI4InwardNode = InwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
|
||||
}
|
||||
|
@ -72,7 +72,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
|
||||
for (bank <- 0 until nBanksPerChannel) {
|
||||
val offset = (bank * nMemoryChannels) + channel
|
||||
ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
|
||||
mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask)))(out)
|
||||
mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask))) := out
|
||||
}
|
||||
mbus
|
||||
}
|
||||
|
@ -24,17 +24,16 @@ case object PeripheryBusKey extends Field[PeripheryBusParams]
|
||||
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
|
||||
|
||||
def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
|
||||
TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
|
||||
TLFragmenter(widthBytes, params.blockBytes) := outwardWWNode
|
||||
}
|
||||
|
||||
def toLargeBurstSlave(maxXferBytes: Int) = {
|
||||
TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode)
|
||||
TLFragmenter(params.beatBytes, maxXferBytes) := outwardBufNode
|
||||
}
|
||||
|
||||
val fromSystemBus: TLInwardNode = {
|
||||
val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
|
||||
inwardBufNode := atomics.node
|
||||
atomics.node
|
||||
}
|
||||
|
||||
def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {
|
||||
|
@ -55,11 +55,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
|
||||
val buffer = LazyModule(new AXI4Buffer)
|
||||
|
||||
memBuses.map(_.toDRAMController).foreach { case node =>
|
||||
converter.node := node
|
||||
trim.node := converter.node
|
||||
yank.node := trim.node
|
||||
buffer.node := yank.node
|
||||
mem_axi4 := buffer.node
|
||||
mem_axi4 := buffer.node := yank.node := trim.node := converter.node := node
|
||||
}
|
||||
}
|
||||
|
||||
@ -97,13 +93,13 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
|
||||
supportsRead = TransferSizes(1, params.maxXferBytes))),
|
||||
beatBytes = params.beatBytes)))
|
||||
|
||||
mmio_axi4 :=
|
||||
AXI4Buffer()(
|
||||
AXI4UserYanker()(
|
||||
AXI4Deinterleaver(sbus.blockBytes)(
|
||||
AXI4IdIndexer(params.idBits)(
|
||||
TLToAXI4()(
|
||||
sbus.toFixedWidthPorts)))))
|
||||
(mmio_axi4
|
||||
:= AXI4Buffer()
|
||||
:= AXI4UserYanker()
|
||||
:= AXI4Deinterleaver(sbus.blockBytes)
|
||||
:= AXI4IdIndexer(params.idBits)
|
||||
:= TLToAXI4()
|
||||
:= sbus.toFixedWidthPorts)
|
||||
}
|
||||
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
@ -132,13 +128,13 @@ trait HasSlaveAXI4Port extends HasSystemBus {
|
||||
id = IdRange(0, 1 << params.idBits))))))
|
||||
|
||||
private val fifoBits = 1
|
||||
sbus.fromSyncPorts() :=
|
||||
TLWidthWidget(params.beatBytes)(
|
||||
AXI4ToTL()(
|
||||
AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))(
|
||||
AXI4Fragmenter()(
|
||||
AXI4IdIndexer(fifoBits)(
|
||||
l2FrontendAXI4Node)))))
|
||||
(sbus.fromSyncPorts()
|
||||
:= TLWidthWidget(params.beatBytes)
|
||||
:= AXI4ToTL()
|
||||
:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
|
||||
:= AXI4Fragmenter()
|
||||
:= AXI4IdIndexer(fifoBits)
|
||||
:= l2FrontendAXI4Node)
|
||||
}
|
||||
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
@ -177,10 +173,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
|
||||
supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
|
||||
beatBytes = params.beatBytes)))
|
||||
|
||||
mmio_tl :=
|
||||
TLBuffer()(
|
||||
TLSourceShrinker(1 << params.idBits)(
|
||||
sbus.toFixedWidthPorts))
|
||||
mmio_tl := TLBuffer() := TLSourceShrinker(1 << params.idBits) := sbus.toFixedWidthPorts
|
||||
}
|
||||
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
@ -215,10 +208,7 @@ trait HasSlaveTLPort extends HasSystemBus {
|
||||
name = "Front Port (TL)",
|
||||
sourceId = IdRange(0, 1 << params.idBits))))))
|
||||
|
||||
sbus.fromSyncPorts() :=
|
||||
TLSourceShrinker(1 << params.sourceBits)(
|
||||
TLWidthWidget(params.beatBytes)(
|
||||
l2FrontendTLNode))
|
||||
sbus.fromSyncPorts() := TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes) := l2FrontendTLNode
|
||||
}
|
||||
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
@ -259,7 +249,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
|
||||
|
||||
for (i <- 0 until channels) {
|
||||
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
|
||||
sram.node := AXI4Buffer()(AXI4Fragmenter()(node))
|
||||
sram.node := AXI4Buffer() := AXI4Fragmenter() := node
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
|
@ -70,24 +70,6 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
|
||||
def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
|
||||
fromSyncPorts(params, name)
|
||||
}
|
||||
|
||||
def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
|
||||
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
|
||||
name.foreach { n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
|
||||
port_fixer.node :=* sink.node
|
||||
sink.node
|
||||
}
|
||||
|
||||
def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
|
||||
|
||||
def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
|
||||
val sink = LazyModule(new TLRationalCrossingSink(dir))
|
||||
name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
|
||||
port_fixer.node :=* sink.node
|
||||
sink.node
|
||||
}
|
||||
|
||||
def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
|
||||
}
|
||||
|
||||
/** Provides buses that serve as attachment points,
|
||||
|
@ -1,12 +0,0 @@
|
||||
// See LICENSE.SiFive for license details.
|
||||
|
||||
package freechips.rocketchip
|
||||
|
||||
import freechips.rocketchip.tilelink.TLOutwardNode
|
||||
import freechips.rocketchip.interrupts.IntOutwardNode
|
||||
|
||||
package object coreplex
|
||||
{
|
||||
implicit class TLCrossableNode(val node: TLOutwardNode)
|
||||
implicit class IntCrossableNode(val node: IntOutwardNode)
|
||||
}
|
@ -393,9 +393,9 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
|
||||
val dmiXbar = LazyModule (new TLXbar())
|
||||
|
||||
val dmOuter = LazyModule( new TLDebugModuleOuter(device))
|
||||
val intnode: IntSyncOutwardNode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
|
||||
val intnode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
|
||||
|
||||
val dmiInnerNode = TLAsyncCrossingSource()(dmiXbar.node)
|
||||
val dmiInnerNode = TLAsyncCrossingSource() := dmiXbar.node
|
||||
|
||||
dmiXbar.node := dmi2tl.node
|
||||
dmOuter.dmiNode := dmiXbar.node
|
||||
@ -1006,7 +1006,7 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
|
||||
|
||||
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents))
|
||||
val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
|
||||
val dmiNode: TLAsyncInwardNode = dmiXing.node
|
||||
val dmiNode = dmiXing.node
|
||||
val tlNode = dmInner.tlNode
|
||||
|
||||
dmInner.dmiNode := dmiXing.node
|
||||
|
@ -67,8 +67,7 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten
|
||||
val model = LazyModule(new TLRAMModel("ZeroDelay"))
|
||||
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := TLDelayer(0.25)(model.node)
|
||||
ram.node := TLDelayer(0.25) := model.node := fuzz.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -7,6 +7,8 @@ import freechips.rocketchip.config.Parameters
|
||||
|
||||
package object diplomacy
|
||||
{
|
||||
type SimpleNodeHandle[D, U, B <: Chisel.Data] = NodeHandle[D, U, B, D, U, B]
|
||||
|
||||
def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
|
||||
case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
|
||||
case _ => ""
|
||||
|
@ -9,7 +9,5 @@ package object interrupts
|
||||
{
|
||||
type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
|
||||
type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
|
||||
type IntNode = NodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool], IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
|
||||
type IntSyncInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]
|
||||
type IntSyncOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]
|
||||
type IntNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
|
||||
}
|
||||
|
@ -122,7 +122,9 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
|
||||
val xbar = LazyModule(new TLXbar)
|
||||
xbar.node := slaveNode
|
||||
xbarPorts.foreach { case (port, bytes) =>
|
||||
port := TLFragmenter(bytes, cacheBlockBytes, earlyAck=true)(if (bytes == xBytes) xbar.node else TLWidthWidget(xBytes)(xbar.node))
|
||||
(Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=true))
|
||||
++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
|
||||
.foldRight(xbar.node:TLOutwardNode)(_ := _)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -60,8 +60,8 @@ class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
|
||||
val module: LazyRoCCModule
|
||||
|
||||
val atlNode: TLMixedNode = TLIdentityNode()
|
||||
val tlNode: TLMixedNode = TLIdentityNode()
|
||||
val atlNode: TLNode = TLIdentityNode()
|
||||
val tlNode: TLNode = TLIdentityNode()
|
||||
}
|
||||
|
||||
class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -68,22 +67,12 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
|
||||
|
||||
object TLAsyncCrossingSource
|
||||
{
|
||||
// applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
|
||||
def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = {
|
||||
val source = LazyModule(new TLAsyncCrossingSource(sync))
|
||||
source.node :=? x
|
||||
source.node
|
||||
}
|
||||
def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSource(sync)).node
|
||||
}
|
||||
|
||||
object TLAsyncCrossingSink
|
||||
{
|
||||
// applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
|
||||
def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
|
||||
sink.node :=? x
|
||||
sink.node
|
||||
}
|
||||
def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSink(depth, sync)).node
|
||||
}
|
||||
|
||||
@deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")
|
||||
@ -119,8 +108,7 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
|
||||
val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
|
||||
ram.node := island.crossTLIn := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -257,12 +256,8 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
|
||||
|
||||
object TLAtomicAutomata
|
||||
{
|
||||
// applied to the TL source node; y.node := TLAtomicAutomata(x.node)
|
||||
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
|
||||
atomics.node :=? x
|
||||
atomics.node
|
||||
}
|
||||
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
|
||||
LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough)).node
|
||||
|
||||
case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
|
||||
|
||||
@ -289,8 +284,13 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
|
||||
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node))))
|
||||
(ram.node
|
||||
:= TLFragmenter(4, 256)
|
||||
:= TLDelayer(0.1)
|
||||
:= TLAtomicAutomata()
|
||||
:= TLDelayer(0.1)
|
||||
:= model.node
|
||||
:= fuzz.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import scala.math.{min,max}
|
||||
@ -57,20 +56,15 @@ class TLBuffer(
|
||||
|
||||
object TLBuffer
|
||||
{
|
||||
// applied to the TL source node; y.node := TLBuffer(x.node)
|
||||
def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(BufferParams.default)(x)
|
||||
def apply(abcde: BufferParams) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
|
||||
def apply(ace: BufferParams, bd: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
|
||||
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
|
||||
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
|
||||
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
|
||||
def apply(
|
||||
a: BufferParams,
|
||||
b: BufferParams,
|
||||
c: BufferParams,
|
||||
d: BufferParams,
|
||||
e: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
|
||||
buffer.node :=? x
|
||||
buffer.node
|
||||
}
|
||||
e: BufferParams)(implicit p: Parameters): TLNode = LazyModule(new TLBuffer(a, b, c, d, e)).node
|
||||
|
||||
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
|
||||
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
|
||||
|
@ -76,50 +76,10 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
|
||||
TLBuffer.chain(addBuffers).foldRight(outwardBufNode)(_ :=? _)
|
||||
}
|
||||
|
||||
def toAsyncSlaves(sync: Int = 3, name: Option[String] = None, addBuffers: Int = 0): TLAsyncOutwardNode = SinkCardinality { implicit p =>
|
||||
val source = LazyModule(new TLAsyncCrossingSource(sync))
|
||||
name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
|
||||
source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
|
||||
}
|
||||
|
||||
def toRationalSlaves(name: Option[String] = None, addBuffers: Int = 0): TLRationalOutwardNode = SinkCardinality { implicit p =>
|
||||
val source = LazyModule(new TLRationalCrossingSource())
|
||||
name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
|
||||
source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
|
||||
}
|
||||
|
||||
def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
|
||||
|
||||
def toAsyncVariableWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
|
||||
val source = LazyModule(new TLAsyncCrossingSource(sync))
|
||||
name.foreach {n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
|
||||
source.node :*= outwardFragNode
|
||||
source.node
|
||||
}
|
||||
|
||||
def toRationalVariableWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
|
||||
val source = LazyModule(new TLRationalCrossingSource())
|
||||
name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
|
||||
source.node :*= outwardFragNode
|
||||
source.node
|
||||
}
|
||||
|
||||
def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
|
||||
|
||||
def toAsyncFixedWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
|
||||
val source = LazyModule(new TLAsyncCrossingSource(sync))
|
||||
name.foreach { n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
|
||||
source.node := outwardWWNode
|
||||
source.node
|
||||
}
|
||||
|
||||
def toRationalFixedWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
|
||||
val source = LazyModule(new TLRationalCrossingSource())
|
||||
name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
|
||||
source.node :*= outwardWWNode
|
||||
source.node
|
||||
}
|
||||
|
||||
def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
|
||||
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import scala.math.{min,max}
|
||||
@ -122,10 +121,5 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
|
||||
|
||||
object TLCacheCork
|
||||
{
|
||||
// applied to the TL source node; y.node := TLCacheCork()(x.node)
|
||||
def apply(unsafe: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val cork = LazyModule(new TLCacheCork(unsafe))
|
||||
cork.node :=? x
|
||||
cork.node
|
||||
}
|
||||
def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode = LazyModule(new TLCacheCork(unsafe)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
@ -73,10 +72,5 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
|
||||
|
||||
object TLDelayer
|
||||
{
|
||||
// applied to the TL source node; y.node := TLDelayer(0.01)(x.node)
|
||||
def apply(q: Double)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val delayer = LazyModule(new TLDelayer(q))
|
||||
delayer.node :=? x
|
||||
delayer.node
|
||||
}
|
||||
def apply(q: Double)(implicit p: Parameters): TLNode = LazyModule(new TLDelayer(q)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import scala.math.max
|
||||
@ -114,10 +113,5 @@ object TLFIFOFixer
|
||||
val allFIFO: Policy = m => m.fifoId.isDefined
|
||||
val allUncacheable: Policy = m => m.regionType <= UNCACHEABLE
|
||||
|
||||
// applied to the TL source node; y.node := TLFIFOFixer()(x.node)
|
||||
def apply(policy: Policy = all)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val fixer = LazyModule(new TLFIFOFixer(policy))
|
||||
fixer.node :=? x
|
||||
fixer.node
|
||||
}
|
||||
def apply(policy: Policy = all)(implicit p: Parameters): TLNode = LazyModule(new TLFIFOFixer(policy)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import scala.math.{min,max}
|
||||
@ -92,9 +91,5 @@ object TLFilter
|
||||
def apply(
|
||||
Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
|
||||
Cfilter: TLClientParameters => Option[TLClientParameters] = TLFilter.Cidentity
|
||||
)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val filter = LazyModule(new TLFilter(Mfilter, Cfilter))
|
||||
filter.node := x
|
||||
filter.node
|
||||
}
|
||||
)(implicit p: Parameters): TLNode = LazyModule(new TLFilter(Mfilter, Cfilter)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -283,12 +282,8 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
|
||||
|
||||
object TLFragmenter
|
||||
{
|
||||
// applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
|
||||
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck))
|
||||
fragmenter.node :=? x
|
||||
fragmenter.node
|
||||
}
|
||||
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: Boolean = false)(implicit p: Parameters): TLNode =
|
||||
LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck)).node
|
||||
}
|
||||
|
||||
/** Synthesizeable unit tests */
|
||||
@ -299,18 +294,18 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
|
||||
val model = LazyModule(new TLRAMModel("Fragmenter"))
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node :=
|
||||
TLDelayer(0.1)(
|
||||
TLBuffer(BufferParams.flow)(
|
||||
TLDelayer(0.1)(
|
||||
TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)(
|
||||
TLDelayer(0.1)(
|
||||
TLBuffer(BufferParams.flow)(
|
||||
TLFragmenter(ramBeatBytes, maxSize/2)(
|
||||
TLDelayer(0.1)(
|
||||
TLBuffer(BufferParams.flow)(
|
||||
model.node)))))))))
|
||||
(ram.node
|
||||
:= TLDelayer(0.1)
|
||||
:= TLBuffer(BufferParams.flow)
|
||||
:= TLDelayer(0.1)
|
||||
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)
|
||||
:= TLDelayer(0.1)
|
||||
:= TLBuffer(BufferParams.flow)
|
||||
:= TLFragmenter(ramBeatBytes, maxSize/2)
|
||||
:= TLDelayer(0.1)
|
||||
:= TLBuffer(BufferParams.flow)
|
||||
:= model.node
|
||||
:= fuzz.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -234,12 +234,11 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
|
||||
val xbar2= LazyModule(new TLXbar)
|
||||
val fuzz = LazyModule(new TLFuzzer(txns))
|
||||
|
||||
model.node := fuzz.node
|
||||
xbar2.node := TLAtomicAutomata()(model.node)
|
||||
ram2.node := TLFragmenter(16, 256)(xbar2.node)
|
||||
xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node))
|
||||
ram.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
|
||||
gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
|
||||
xbar2.node := TLAtomicAutomata() := model.node := fuzz.node
|
||||
ram2.node := TLFragmenter(16, 256) := xbar2.node
|
||||
xbar.node := TLWidthWidget(16) := TLHintHandler() := xbar2.node
|
||||
ram.node := TLFragmenter(4, 256) := TLBuffer() := xbar.node
|
||||
gpio.node := TLFragmenter(4, 32) := TLBuffer() := xbar.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import scala.math.min
|
||||
@ -92,12 +91,8 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
|
||||
|
||||
object TLHintHandler
|
||||
{
|
||||
// applied to the TL source node; y.node := TLHintHandler(x.node)
|
||||
def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
|
||||
hints.node :=? x
|
||||
hints.node
|
||||
}
|
||||
def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
|
||||
LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough)).node
|
||||
}
|
||||
|
||||
/** Synthesizeable unit tests */
|
||||
@ -110,8 +105,13 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val model = LazyModule(new TLRAMModel("HintHandler"))
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node))))
|
||||
(ram.node
|
||||
:= TLFragmenter(4, 256)
|
||||
:= TLDelayer(0.1)
|
||||
:= TLHintHandler()
|
||||
:= TLDelayer(0.1)
|
||||
:= model.node
|
||||
:= fuzz.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util.AsyncBundle
|
||||
@ -67,17 +66,3 @@ class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implici
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
object TLIsolation
|
||||
{
|
||||
// applied to the TL source node; y.node := TLIsolation(fOut, fIn)(x.node)
|
||||
// f* should insert an isolation gate between the input UInt and its result
|
||||
// fOut is applied to data flowing from client to manager
|
||||
// fIn is applied to data flowing from manager to client
|
||||
// **** WARNING: the isolation functions must bring the values to 0 ****
|
||||
def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
|
||||
val iso = LazyModule(new TLIsolation(fOut, fIn))
|
||||
iso.node :=? x
|
||||
(iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))
|
||||
}
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import scala.math.{min,max}
|
||||
@ -39,10 +38,5 @@ class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
|
||||
|
||||
object TLMap
|
||||
{
|
||||
// applied to the TL source node; y.node := TLMap(fn)(x.node)
|
||||
def apply(fn: AddressSet => BigInt)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val map = LazyModule(new TLMap(fn))
|
||||
map.node :=? x
|
||||
map.node
|
||||
}
|
||||
def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode = LazyModule(new TLMap(fn)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
@ -56,10 +55,5 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete
|
||||
|
||||
object TLNodeNumberer
|
||||
{
|
||||
// applied to the TL source node; y.node := TLBuffer(x.node)
|
||||
def apply(nodeAddressOffset: Option[Int] = None)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val numberer = LazyModule(new TLNodeNumberer(nodeAddressOffset))
|
||||
numberer.node :=? x
|
||||
numberer.node
|
||||
}
|
||||
def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode = LazyModule(new TLNodeNumberer(nodeAddressOffset)).node
|
||||
}
|
||||
|
@ -10,7 +10,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -79,22 +78,12 @@ class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit
|
||||
|
||||
object TLRationalCrossingSource
|
||||
{
|
||||
// applied to the TL source node; y.node := TLRationalCrossingSource()(x.node)
|
||||
def apply()(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLRationalOutwardNode = {
|
||||
val source = LazyModule(new TLRationalCrossingSource)
|
||||
source.node :=? x
|
||||
source.node
|
||||
}
|
||||
def apply()(implicit p: Parameters) = LazyModule(new TLRationalCrossingSource).node
|
||||
}
|
||||
|
||||
object TLRationalCrossingSink
|
||||
{
|
||||
// applied to the TL source node; y.node := TLRationalCrossingSink()(x.node)
|
||||
def apply(direction: RationalDirection = Symmetric)(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val sink = LazyModule(new TLRationalCrossingSink(direction))
|
||||
sink.node :=? x
|
||||
sink.node
|
||||
}
|
||||
def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) = LazyModule(new TLRationalCrossingSink(direction)).node
|
||||
}
|
||||
|
||||
@deprecated("TLRationalCrossing is fragile. Use TLRationalCrossingSource and TLRationalCrossingSink", "rocket-chip 1.2")
|
||||
@ -129,8 +118,11 @@ class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameter
|
||||
val fuzz = LazyModule(new TLFuzzer(txns))
|
||||
val model = LazyModule(new TLRAMModel(name))
|
||||
|
||||
model.node := fuzz.node
|
||||
node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node))
|
||||
(node
|
||||
:= TLRationalCrossingSource()
|
||||
:= TLDelayer(0.25)
|
||||
:= model.node
|
||||
:= fuzz.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = IO(new Bundle {
|
||||
@ -144,7 +136,11 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
|
||||
val node = TLRationalIdentityNode()
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.25)(TLRationalCrossingSink(direction)(node)))
|
||||
(ram.node
|
||||
:= TLFragmenter(4, 256)
|
||||
:= TLDelayer(0.25)
|
||||
:= TLRationalCrossingSink(direction)
|
||||
:= node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) { }
|
||||
}
|
||||
|
@ -260,7 +260,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(txns))
|
||||
val rrtr = LazyModule(new RRTest0(0x400))
|
||||
|
||||
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
|
||||
rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
@ -275,7 +275,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(txns))
|
||||
val rrtr = LazyModule(new RRTest1(0x400))
|
||||
|
||||
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
|
||||
rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -89,8 +89,7 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
|
||||
val model = LazyModule(new TLRAMModel("SRAMSimple"))
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := TLDelayer(0.25)(model.node)
|
||||
ram.node := TLDelayer(0.25) := model.node := fuzz.node
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -75,10 +74,5 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
|
||||
|
||||
object TLSourceShrinker
|
||||
{
|
||||
// applied to the TL source node; y.node := TLSourceShrinker(n)(x.node)
|
||||
def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
|
||||
shrinker.node :=? x
|
||||
shrinker.node
|
||||
}
|
||||
def apply(maxInFlight: Int)(implicit p: Parameters): TLNode = LazyModule(new TLSourceShrinker(maxInFlight)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.amba.ahb._
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
@ -187,10 +186,5 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
|
||||
|
||||
object TLToAHB
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAHB()(x.node)
|
||||
def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
|
||||
val ahb = LazyModule(new TLToAHB(aFlow))
|
||||
ahb.node :=? x
|
||||
ahb.node
|
||||
}
|
||||
def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAHB(aFlow)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.amba.apb._
|
||||
@ -86,10 +85,5 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
|
||||
|
||||
object TLToAPB
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAPB()(x.node)
|
||||
def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): APBOutwardNode = {
|
||||
val apb = LazyModule(new TLToAPB(aFlow))
|
||||
apb.node :=? x
|
||||
apb.node
|
||||
}
|
||||
def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAPB(aFlow)).node
|
||||
}
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -215,12 +214,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
|
||||
|
||||
object TLToAXI4
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAXI4()(x.node)
|
||||
def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
|
||||
val axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits))
|
||||
axi4.node :=? x
|
||||
axi4.node
|
||||
}
|
||||
def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) =
|
||||
LazyModule(new TLToAXI4(combinational, adapterName, stripBits)).node
|
||||
|
||||
def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
|
||||
if ( a.supportsProbe && !b.supportsProbe) return false
|
||||
|
@ -3,7 +3,6 @@
|
||||
package freechips.rocketchip.tilelink
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util._
|
||||
@ -192,12 +191,7 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
|
||||
|
||||
object TLWidthWidget
|
||||
{
|
||||
// applied to the TL source node; y.node := WidthWidget(x.node, 16)
|
||||
def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
|
||||
widget.node :=? x
|
||||
widget.node
|
||||
}
|
||||
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = LazyModule(new TLWidthWidget(innerBeatBytes)).node
|
||||
}
|
||||
|
||||
/** Synthesizeable unit tests */
|
||||
@ -208,12 +202,14 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
|
||||
val model = LazyModule(new TLRAMModel("WidthWidget"))
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
|
||||
model.node := fuzz.node
|
||||
ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)(
|
||||
if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) }
|
||||
else {
|
||||
TLWidthWidget(second)(
|
||||
TLWidthWidget(first)(TLDelayer(0.1)(model.node)))}))
|
||||
(ram.node
|
||||
:= TLDelayer(0.1)
|
||||
:= TLFragmenter(4, 256)
|
||||
:= TLWidthWidget(second)
|
||||
:= TLWidthWidget(first)
|
||||
:= TLDelayer(0.1)
|
||||
:= model.node
|
||||
:= fuzz.node)
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
io.finished := fuzz.module.io.finished
|
||||
|
@ -256,11 +256,10 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
|
||||
val model = LazyModule(new TLRAMModel("Xbar"))
|
||||
val xbar = LazyModule(new TLXbar)
|
||||
|
||||
model.node := fuzz.node
|
||||
xbar.node := TLDelayer(0.1)(model.node)
|
||||
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
|
||||
(0 until nManagers) foreach { n =>
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
|
||||
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
@ -277,13 +276,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
|
||||
|
||||
val fuzzers = (0 until nClients) map { n =>
|
||||
val fuzz = LazyModule(new TLFuzzer(txns))
|
||||
xbar.node := TLDelayer(0.1)(fuzz.node)
|
||||
xbar.node := TLDelayer(0.1) := fuzz.node
|
||||
fuzz
|
||||
}
|
||||
|
||||
(0 until nManagers) foreach { n =>
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
|
||||
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
|
||||
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) with UnitTestModule {
|
||||
|
@ -9,11 +9,5 @@ package object tilelink
|
||||
{
|
||||
type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
|
||||
type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
|
||||
type TLNode = NodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle, TLClientPortParameters, TLManagerPortParameters, TLBundle]
|
||||
type TLAsyncInwardNode = InwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
|
||||
type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
|
||||
type TLRationalInwardNode = InwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
|
||||
type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
|
||||
type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle,
|
||||
TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle]
|
||||
type TLNode = SimpleNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user