Merge pull request #1077 from freechipsproject/node-style

diplomacy: switch adapter methods to node style

src/main/scala/amba/ahb/Test.scala

@@ -25,8 +25,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
   val ram   = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
   val gpio  = LazyModule(new RRTest0(0x100))
 
-  model.node := fuzz.node
+  xbar.node := TLToAHB(aFlow) := TLDelayer(0.1) := model.node := fuzz.node
-  xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node))
   ram.node  := xbar.node
   gpio.node := xbar.node
 
@@ -46,13 +45,13 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
   val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
 
-  model.node := fuzz.node
+  (node
-  node :=
+     := TLToAHB(aFlow)
-    TLToAHB(aFlow)(
+     := TLDelayer(0.2)
-    TLDelayer(0.2)(
+     := TLBuffer(BufferParams.flow)
-    TLBuffer(BufferParams.flow)(
+     := TLDelayer(0.2)
-    TLDelayer(0.2)(
+     := model.node
-    model.node))))
+     := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {
@@ -68,13 +67,13 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
   val node = AHBIdentityNode()
   val ram  = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
 
-  ram.node :=
+  (ram.node
-    TLFragmenter(4, 16)(
+    := TLFragmenter(4, 16)
-    TLDelayer(0.2)(
+    := TLDelayer(0.2)
-    TLBuffer(BufferParams.flow)(
+    := TLBuffer(BufferParams.flow)
-    TLDelayer(0.2)(
+    := TLDelayer(0.2)
-    AHBToTL()(
+    := AHBToTL()
-    node)))))
+    := node)
 
   lazy val module = new LazyModuleImp(this) { }
 }

src/main/scala/amba/ahb/ToTL.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.ahb
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -132,9 +131,5 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule
 
 object AHBToTL
 {
-  def apply()(x: AHBOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+  def apply()(implicit p: Parameters) = LazyModule(new AHBToTL).node
-    val tl = LazyModule(new AHBToTL)
-    tl.node :=? x
-    tl.node
-  }
 }

src/main/scala/amba/ahb/package.scala

@@ -3,9 +3,11 @@
 package freechips.rocketchip.amba
 
 import Chisel._
-import freechips.rocketchip.diplomacy.OutwardNodeHandle
+import freechips.rocketchip.diplomacy._
 
 package object ahb
 {
   type AHBOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
+  type AHBInwardNode = InwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
+  type AHBNode = SimpleNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
 }

src/main/scala/amba/apb/Test.scala

@@ -24,15 +24,15 @@ class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
   val ram   = LazyModule(new APBRAM(AddressSet(0x0, 0xff)))
   val gpio  = LazyModule(new RRTest0(0x100))
 
-  model.node := fuzz.node
   ram.node  := xbar.node
   gpio.node := xbar.node
-  xbar.node :=
+  (xbar.node
-    TLToAPB(aFlow)(
+    := TLToAPB(aFlow)
-    TLDelayer(0.2)(
+    := TLDelayer(0.2)
-    TLBuffer(BufferParams.flow)(
+    := TLBuffer(BufferParams.flow)
-    TLDelayer(0.2)(
+    := TLDelayer(0.2)
-    model.node))))
+    := model.node
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/amba/apb/package.scala

@@ -3,9 +3,11 @@
 package freechips.rocketchip.amba
 
 import Chisel._
-import freechips.rocketchip.diplomacy.OutwardNodeHandle
+import freechips.rocketchip.diplomacy._
 
 package object apb
 {
   type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
+  type APBInwardNode = InwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
+  type APBNode = SimpleNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBBundle]
 }

src/main/scala/amba/axi4/AsyncCrossing.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -44,22 +43,12 @@ class AXI4AsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameter
 
 object AXI4AsyncCrossingSource
 {
-  // applied to the AXI4 source node; y.node := AXI4AsyncCrossingSource()(x.node)
+  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSource(sync)).node
-  def apply(sync: Int = 3)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4AsyncOutwardNode = {
-    val source = LazyModule(new AXI4AsyncCrossingSource(sync))
-    source.node :=? x
-    source.node
-  }
 }
 
 object AXI4AsyncCrossingSink
 {
-  // applied to the AXI4 source node; y.node := AXI4AsyncCrossingSink()(x.node)
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new AXI4AsyncCrossingSink(depth, sync)).node
-  def apply(depth: Int = 8, sync: Int = 3)(x: AXI4AsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val sink = LazyModule(new AXI4AsyncCrossingSink(depth, sync))
-    sink.node :=? x
-    sink.node
-  }
 }
 
 @deprecated("AXI4AsyncCrossing is fragile. Use AXI4AsyncCrossingSource and AXI4AsyncCrossingSink", "rocket-chip 1.2")

src/main/scala/amba/axi4/Buffer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -46,18 +45,13 @@ class AXI4Buffer(
 
 object AXI4Buffer
 {
-  // applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
+  def apply()                                  (implicit p: Parameters): AXI4Node = apply(BufferParams.default)
-  def apply()                                  (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(BufferParams.default)(x)
+  def apply(z: BufferParams)                   (implicit p: Parameters): AXI4Node = apply(z, z)
-  def apply(z: BufferParams)                   (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(z, z)(x)
+  def apply(aw: BufferParams, br: BufferParams)(implicit p: Parameters): AXI4Node = apply(aw, aw, br, aw, br)
-  def apply(aw: BufferParams, br: BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br)(x)
   def apply(
     aw: BufferParams,
     w:  BufferParams,
     b:  BufferParams,
     ar: BufferParams,
-    r:  BufferParams)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
+    r:  BufferParams)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Buffer(aw, w, b, ar, r)).node
-    val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r))
-    buffer.node :=? x
-    buffer.node
-  }
 }

src/main/scala/amba/axi4/Deinterleaver.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -100,10 +99,5 @@ class AXI4Deinterleaver(maxReadBytes: Int)(implicit p: Parameters) extends LazyM
 
 object AXI4Deinterleaver
 {
-  // applied to the AXI4 source node; y.node := AXI4Deinterleaver()(x.node)
+  def apply(maxReadBytes: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Deinterleaver(maxReadBytes)).node
-  def apply(maxReadBytes: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val deinterleaver = LazyModule(new AXI4Deinterleaver(maxReadBytes))
-    deinterleaver.node :=? x
-    deinterleaver.node
-  }
 }

src/main/scala/amba/axi4/Fragmenter.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -200,10 +199,5 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
 object AXI4Fragmenter
 {
-  // applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
+  def apply()(implicit p: Parameters): AXI4Node = LazyModule(new AXI4Fragmenter).node
-  def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val fragmenter = LazyModule(new AXI4Fragmenter)
-    fragmenter.node :=? x
-    fragmenter.node
-  }
 }

src/main/scala/amba/axi4/IdIndexer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -76,10 +75,5 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
 
 object AXI4IdIndexer
 {
-  // applied to the AXI4 source node; y.node := AXI4IdIndexer(idBits)(x.node)
+  def apply(idBits: Int)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4IdIndexer(idBits)).node
-  def apply(idBits: Int)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val indexer = LazyModule(new AXI4IdIndexer(idBits))
-    indexer.node :=? x
-    indexer.node
-  }
 }

src/main/scala/amba/axi4/Test.scala

@@ -25,10 +25,9 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
   val gpio  = LazyModule(new RRTest1(0x400))
   val ram   = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
 
-  model.node := fuzz.node
+  xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node
-  xbar.node  := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
+  ram.node  := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(true ) := TLFragmenter(4, 16) := xbar.node
-  ram.node   := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(true )(TLFragmenter(4, 16)(xbar.node))))
+  gpio.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(false) := TLFragmenter(4, 16) := xbar.node
-  gpio.node  := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(false)(TLFragmenter(4, 16)(xbar.node))))
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished
@@ -48,10 +47,9 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
   val gpio  = LazyModule(new RRTest0(0x400))
   val ram   = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
 
-  model.node := fuzz.node
+  xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node
-  xbar.node  := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node)))
+  ram.node  := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(false) := xbar.node
-  ram.node   := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(false)(xbar.node)))
+  gpio.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(true ) := xbar.node
-  gpio.node  := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(true )(xbar.node)))
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished
@@ -73,15 +71,15 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with
   val fuzz  = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
   val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
 
-  model.node := fuzz.node
+  (node
-  node :=
+    := AXI4UserYanker()
-    AXI4UserYanker()(
+    := AXI4Deinterleaver(64)
-    AXI4Deinterleaver(64)(
+    := TLToAXI4()
-    TLToAXI4()(
+    := TLDelayer(0.1)
-    TLDelayer(0.1)(
+    := TLBuffer(BufferParams.flow)
-    TLBuffer(BufferParams.flow)(
+    := TLDelayer(0.1)
-    TLDelayer(0.1)(
+    := model.node
-    model.node))))))
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {
@@ -99,19 +97,19 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
   val ram  = LazyModule(new TLRAM(fuzzAddr))
   val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
 
-  ram.node   := TLFragmenter(4, 16)(xbar.node)
+  ram.node   := TLFragmenter(4, 16) := xbar.node
   error.node := xbar.node
 
-  xbar.node :=
+  (xbar.node
-    TLFIFOFixer()(
+    := TLFIFOFixer()
-    TLDelayer(0.1)(
+    := TLDelayer(0.1)
-    TLBuffer(BufferParams.flow)(
+    := TLBuffer(BufferParams.flow)
-    TLDelayer(0.1)(
+    := TLDelayer(0.1)
-    AXI4ToTL()(
+    := AXI4ToTL()
-    AXI4UserYanker(Some(4))(
+    := AXI4UserYanker(Some(4))
-    AXI4Fragmenter()(
+    := AXI4Fragmenter()
-    AXI4IdIndexer(2)(
+    := AXI4IdIndexer(2)
-    node))))))))
+    := node)
 
   lazy val module = new LazyModuleImp(this) { }
 }

src/main/scala/amba/axi4/ToTL.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -161,9 +160,5 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
 
 object AXI4ToTL
 {
-  def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+  def apply()(implicit p: Parameters) = LazyModule(new AXI4ToTL).node
-    val tl = LazyModule(new AXI4ToTL)
-    tl.node :=? x
-    tl.node
-  }
 }

src/main/scala/amba/axi4/UserYanker.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.axi4
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.UIntToOH1
@@ -92,10 +91,5 @@ class AXI4UserYanker(capMaxFlight: Option[Int] = None)(implicit p: Parameters) e
 
 object AXI4UserYanker
 {
-  // applied to the AXI4 source node; y.node := AXI4UserYanker(idBits, maxFlight)(x.node)
+  def apply(capMaxFlight: Option[Int] = None)(implicit p: Parameters): AXI4Node = LazyModule(new AXI4UserYanker(capMaxFlight)).node
-  def apply(capMaxFlight: Option[Int] = None)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
-    val yanker = LazyModule(new AXI4UserYanker(capMaxFlight))
-    yanker.node :=? x
-    yanker.node
-  }
 }

src/main/scala/amba/axi4/package.scala

@@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
 
 package object axi4
 {
+  type AXI4Node = SimpleNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
   type AXI4OutwardNode = OutwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
-  type AXI4AsyncOutwardNode = OutwardNodeHandle[AXI4AsyncMasterPortParameters, AXI4AsyncSlavePortParameters, AXI4AsyncBundle]
+  type AXI4InwardNode = InwardNodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
-  type AXI4Node = NodeHandle[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle, AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4Bundle]
 }

src/main/scala/coreplex/MemoryBus.scala

@@ -72,7 +72,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
     for (bank <- 0 until nBanksPerChannel) {
       val offset = (bank * nMemoryChannels) + channel
       ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
-      mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask)))(out)
+      mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask))) := out
     }
     mbus
   }

src/main/scala/coreplex/PeripheryBus.scala

@@ -24,17 +24,16 @@ case object PeripheryBusKey extends Field[PeripheryBusParams]
 class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
 
   def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
-    TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
+    TLFragmenter(widthBytes, params.blockBytes) := outwardWWNode
   }
 
   def toLargeBurstSlave(maxXferBytes: Int) = {
-    TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode)
+    TLFragmenter(params.beatBytes, maxXferBytes) := outwardBufNode
   }
 
   val fromSystemBus: TLInwardNode = {
     val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
     inwardBufNode := atomics.node
-    atomics.node
   }
 
   def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {

src/main/scala/coreplex/Ports.scala

@@ -55,11 +55,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
   val buffer = LazyModule(new AXI4Buffer)
 
   memBuses.map(_.toDRAMController).foreach { case node =>
-    converter.node := node
+    mem_axi4 := buffer.node := yank.node := trim.node := converter.node := node
-    trim.node := converter.node
-    yank.node := trim.node
-    buffer.node := yank.node
-    mem_axi4 := buffer.node
   }
 }
 
@@ -97,13 +93,13 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
       supportsRead  = TransferSizes(1, params.maxXferBytes))),
     beatBytes = params.beatBytes)))
 
-  mmio_axi4 :=
+  (mmio_axi4
-    AXI4Buffer()(
+    := AXI4Buffer()
-    AXI4UserYanker()(
+    := AXI4UserYanker()
-    AXI4Deinterleaver(sbus.blockBytes)(
+    := AXI4Deinterleaver(sbus.blockBytes)
-    AXI4IdIndexer(params.idBits)(
+    := AXI4IdIndexer(params.idBits)
-    TLToAXI4()(
+    := TLToAXI4()
-    sbus.toFixedWidthPorts)))))
+    := sbus.toFixedWidthPorts)
 }
 
 /** Common io name and methods for propagating or tying off the port bundle */
@@ -132,13 +128,13 @@ trait HasSlaveAXI4Port extends HasSystemBus {
       id   = IdRange(0, 1 << params.idBits))))))
 
   private val fifoBits = 1
-  sbus.fromSyncPorts() :=
+  (sbus.fromSyncPorts()
-    TLWidthWidget(params.beatBytes)(
+    := TLWidthWidget(params.beatBytes)
-    AXI4ToTL()(
+    := AXI4ToTL()
-    AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))(
+    := AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
-    AXI4Fragmenter()(
+    := AXI4Fragmenter()
-    AXI4IdIndexer(fifoBits)(
+    := AXI4IdIndexer(fifoBits)
-    l2FrontendAXI4Node)))))
+    := l2FrontendAXI4Node)
 }
 
 /** Common io name and methods for propagating or tying off the port bundle */
@@ -177,10 +173,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
       supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
     beatBytes = params.beatBytes)))
 
-  mmio_tl :=
+  mmio_tl := TLBuffer() := TLSourceShrinker(1 << params.idBits) := sbus.toFixedWidthPorts
-    TLBuffer()(
-    TLSourceShrinker(1 << params.idBits)(
-    sbus.toFixedWidthPorts))
 }
 
 /** Common io name and methods for propagating or tying off the port bundle */
@@ -215,10 +208,7 @@ trait HasSlaveTLPort extends HasSystemBus {
       name     = "Front Port (TL)",
       sourceId = IdRange(0, 1 << params.idBits))))))
 
-  sbus.fromSyncPorts() :=
+  sbus.fromSyncPorts() := TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes) := l2FrontendTLNode
-    TLSourceShrinker(1 << params.sourceBits)(
-    TLWidthWidget(params.beatBytes)(
-    l2FrontendTLNode))
 }
 
 /** Common io name and methods for propagating or tying off the port bundle */
@@ -259,7 +249,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
 
   for (i <- 0 until channels) {
     val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
-    sram.node := AXI4Buffer()(AXI4Fragmenter()(node))
+    sram.node := AXI4Buffer() := AXI4Fragmenter() := node
   }
 
   lazy val module = new LazyModuleImp(this) {

src/main/scala/coreplex/SystemBus.scala

@@ -70,24 +70,6 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
     fromSyncPorts(params, name)
   }
-
-  def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
-    val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    name.foreach { n => sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
-    port_fixer.node :=* sink.node
-    sink.node
-  }
-
-  def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
-
-  def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
-    val sink = LazyModule(new TLRationalCrossingSink(dir))
-    name.foreach{ n => sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
-    port_fixer.node :=* sink.node
-    sink.node
-  }
-
-  def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
 }
 
 /** Provides buses that serve as attachment points,

src/main/scala/coreplex/package.scala

@@ -1,12 +0,0 @@
-// See LICENSE.SiFive for license details.
-
-package freechips.rocketchip
-
-import freechips.rocketchip.tilelink.TLOutwardNode
-import freechips.rocketchip.interrupts.IntOutwardNode
-
-package object coreplex
-{
-  implicit class TLCrossableNode(val node: TLOutwardNode)
-  implicit class IntCrossableNode(val node: IntOutwardNode)
-}

src/main/scala/devices/debug/Debug.scala

@@ -393,9 +393,9 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
   val dmiXbar = LazyModule (new TLXbar())
 
   val dmOuter = LazyModule( new TLDebugModuleOuter(device))
-  val intnode: IntSyncOutwardNode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
+  val intnode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
 
-  val dmiInnerNode = TLAsyncCrossingSource()(dmiXbar.node)
+  val dmiInnerNode = TLAsyncCrossingSource() := dmiXbar.node
 
   dmiXbar.node := dmi2tl.node
   dmOuter.dmiNode := dmiXbar.node
@@ -1006,7 +1006,7 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
 
   val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents))
   val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
-  val dmiNode: TLAsyncInwardNode = dmiXing.node
+  val dmiNode = dmiXing.node
   val tlNode = dmInner.tlNode
 
   dmInner.dmiNode := dmiXing.node

src/main/scala/devices/tilelink/TestRAM.scala

@@ -67,8 +67,7 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten
   val model = LazyModule(new TLRAMModel("ZeroDelay"))
   val ram  = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
-  model.node := fuzz.node
+  ram.node := TLDelayer(0.25) := model.node := fuzz.node
-  ram.node := TLDelayer(0.25)(model.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/diplomacy/package.scala

@@ -7,6 +7,8 @@ import freechips.rocketchip.config.Parameters
 
 package object diplomacy
 {
+  type SimpleNodeHandle[D, U, B <: Chisel.Data] = NodeHandle[D, U, B, D, U, B]
+
   def sourceLine(sourceInfo: SourceInfo, prefix: String = " (", suffix: String = ")") = sourceInfo match {
     case SourceLine(filename, line, col) => s"$prefix$filename:$line:$col$suffix"
     case _ => ""

src/main/scala/interrupts/package.scala

@@ -9,7 +9,5 @@ package object interrupts
 {
   type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
   type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
-  type IntNode = NodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool], IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
+  type IntNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
-  type IntSyncInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]
-  type IntSyncOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, SyncInterrupts]
 }

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -122,7 +122,9 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
       val xbar = LazyModule(new TLXbar)
       xbar.node := slaveNode
       xbarPorts.foreach { case (port, bytes) =>
-        port := TLFragmenter(bytes, cacheBlockBytes, earlyAck=true)(if (bytes == xBytes) xbar.node else TLWidthWidget(xBytes)(xbar.node))
+        (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=true))
+          ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
+          .foldRight(xbar.node:TLOutwardNode)(_ := _)
       }
     }
   }

src/main/scala/tile/LazyRoCC.scala

@@ -60,8 +60,8 @@ class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
 abstract class LazyRoCC(implicit p: Parameters) extends LazyModule {
   val module: LazyRoCCModule
 
-  val atlNode: TLMixedNode = TLIdentityNode()
+  val atlNode: TLNode = TLIdentityNode()
-  val tlNode: TLMixedNode = TLIdentityNode()
+  val tlNode: TLNode = TLIdentityNode()
 }
 
 class RoCCIO(outer: LazyRoCC)(implicit p: Parameters) extends RoCCCoreIO()(p) {

src/main/scala/tilelink/AsyncCrossing.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -68,22 +67,12 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
 
 object TLAsyncCrossingSource
 {
-  // applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
+  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSource(sync)).node
-  def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = {
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    source.node :=? x
-    source.node
-  }
 }
 
 object TLAsyncCrossingSink
 {
-  // applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
+  def apply(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) = LazyModule(new TLAsyncCrossingSink(depth, sync)).node
-  def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
-    sink.node :=? x
-    sink.node
-  }
 }
 
 @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2")
@@ -119,8 +108,7 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
   val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
   val ram  = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
 
-  model.node := fuzz.node
+  ram.node := island.crossTLIn := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node
-  ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/AtomicAutomata.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -257,12 +256,8 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
 
 object TLAtomicAutomata
 {
-  // applied to the TL source node; y.node := TLAtomicAutomata(x.node)
+  def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-  def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough)).node
-    val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
-    atomics.node :=? x
-    atomics.node
-  }
 
   case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int)
 
@@ -289,8 +284,13 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
   val model = LazyModule(new TLRAMModel("AtomicAutomata"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
-  model.node := fuzz.node
+  (ram.node
-  ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node))))
+    := TLFragmenter(4, 256)
+    := TLDelayer(0.1)
+    := TLAtomicAutomata()
+    := TLDelayer(0.1)
+    := model.node
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/Buffer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -57,20 +56,15 @@ class TLBuffer(
 
 object TLBuffer
 {
-  // applied to the TL source node; y.node := TLBuffer(x.node)
+  def apply()                                   (implicit p: Parameters): TLNode = apply(BufferParams.default)
-  def apply()                                   (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(BufferParams.default)(x)
+  def apply(abcde: BufferParams)                (implicit p: Parameters): TLNode = apply(abcde, abcde)
-  def apply(abcde: BufferParams)                (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(abcde, abcde)(x)
+  def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
-  def apply(ace: BufferParams, bd: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace)(x)
   def apply(
       a: BufferParams,
       b: BufferParams,
       c: BufferParams,
       d: BufferParams,
-      e: BufferParams)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+      e: BufferParams)(implicit p: Parameters): TLNode = LazyModule(new TLBuffer(a, b, c, d, e)).node
-    val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
-    buffer.node :=? x
-    buffer.node
-  }
 
   def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
     val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }

src/main/scala/tilelink/Bus.scala

@@ -76,50 +76,10 @@ abstract class TLBusWrapper(params: TLBusParams, val busName: String)(implicit p
     TLBuffer.chain(addBuffers).foldRight(outwardBufNode)(_ :=? _)
   }
 
-  def toAsyncSlaves(sync: Int = 3, name: Option[String] = None, addBuffers: Int = 0): TLAsyncOutwardNode = SinkCardinality { implicit p =>
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
-    source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
-  }
-
-  def toRationalSlaves(name: Option[String] = None, addBuffers: Int = 0): TLRationalOutwardNode = SinkCardinality { implicit p =>
-    val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
-    source.node :=? TLBuffer.chain(addBuffers).foldRight(outwardNode)(_ :=? _)
-  }
-
   def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
 
-  def toAsyncVariableWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach {n =>  source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
-    source.node :*= outwardFragNode
-    source.node
-  }
-
-  def toRationalVariableWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
-    val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach {n =>  source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
-    source.node :*= outwardFragNode
-    source.node
-  }
-
   def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
 
-  def toAsyncFixedWidthSlaves(sync: Int = 3, name: Option[String] = None): TLAsyncOutwardNode = {
-    val source = LazyModule(new TLAsyncCrossingSource(sync))
-    name.foreach { n => source.suggestName(s"${busName}_${name}_TLAsyncCrossingSource")}
-    source.node := outwardWWNode
-    source.node
-  }
-
-  def toRationalFixedWidthSlaves(name: Option[String] = None): TLRationalOutwardNode = {
-    val source = LazyModule(new TLRationalCrossingSource())
-    name.foreach {n => source.suggestName(s"${busName}_${name}_TLRationalCrossingSource")}
-    source.node :*= outwardWWNode
-    source.node
-  }
-
   def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
 
 }

src/main/scala/tilelink/CacheCork.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -122,10 +121,5 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
 
 object TLCacheCork
 {
-  // applied to the TL source node; y.node := TLCacheCork()(x.node)
+  def apply(unsafe: Boolean = false)(implicit p: Parameters): TLNode = LazyModule(new TLCacheCork(unsafe)).node
-  def apply(unsafe: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val cork = LazyModule(new TLCacheCork(unsafe))
-    cork.node :=? x
-    cork.node
-  }
 }

src/main/scala/tilelink/Delayer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 
@@ -73,10 +72,5 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule
 
 object TLDelayer
 {
-  // applied to the TL source node; y.node := TLDelayer(0.01)(x.node)
+  def apply(q: Double)(implicit p: Parameters): TLNode = LazyModule(new TLDelayer(q)).node
-  def apply(q: Double)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val delayer = LazyModule(new TLDelayer(q))
-    delayer.node :=? x
-    delayer.node
-  }
 }

src/main/scala/tilelink/FIFOFixer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.max
@@ -114,10 +113,5 @@ object TLFIFOFixer
   val allFIFO:        Policy = m => m.fifoId.isDefined
   val allUncacheable: Policy = m => m.regionType <= UNCACHEABLE
 
-  // applied to the TL source node; y.node := TLFIFOFixer()(x.node)
+  def apply(policy: Policy = all)(implicit p: Parameters): TLNode = LazyModule(new TLFIFOFixer(policy)).node
-  def apply(policy: Policy = all)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val fixer = LazyModule(new TLFIFOFixer(policy))
-    fixer.node :=? x
-    fixer.node
-  }
 }

src/main/scala/tilelink/Filter.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -92,9 +91,5 @@ object TLFilter
   def apply(
     Mfilter: TLManagerParameters => Option[TLManagerParameters] = TLFilter.Midentity,
     Cfilter: TLClientParameters  => Option[TLClientParameters]  = TLFilter.Cidentity
-    )(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    )(implicit p: Parameters): TLNode = LazyModule(new TLFilter(Mfilter, Cfilter)).node
-    val filter = LazyModule(new TLFilter(Mfilter, Cfilter))
-    filter.node := x
-    filter.node
-  }
 }

src/main/scala/tilelink/Fragmenter.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -283,12 +282,8 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
 
 object TLFragmenter
 {
-  // applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
+  def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: Boolean = false)(implicit p: Parameters): TLNode =
-  def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck)).node
-    val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck))
-    fragmenter.node :=? x
-    fragmenter.node
-  }
 }
 
 /** Synthesizeable unit tests */
@@ -299,18 +294,18 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
   val model = LazyModule(new TLRAMModel("Fragmenter"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
-  model.node := fuzz.node
+  (ram.node
-  ram.node :=
+    := TLDelayer(0.1)
-    TLDelayer(0.1)(
+    := TLBuffer(BufferParams.flow)
-    TLBuffer(BufferParams.flow)(
+    := TLDelayer(0.1)
-    TLDelayer(0.1)(
+    := TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)
-    TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)(
+    := TLDelayer(0.1)
-    TLDelayer(0.1)(
+    := TLBuffer(BufferParams.flow)
-    TLBuffer(BufferParams.flow)(
+    := TLFragmenter(ramBeatBytes, maxSize/2)
-    TLFragmenter(ramBeatBytes, maxSize/2)(
+    := TLDelayer(0.1)
-    TLDelayer(0.1)(
+    := TLBuffer(BufferParams.flow)
-    TLBuffer(BufferParams.flow)(
+    := model.node
-    model.node)))))))))
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/Fuzzer.scala

@@ -234,12 +234,11 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
   val xbar2= LazyModule(new TLXbar)
   val fuzz = LazyModule(new TLFuzzer(txns))
 
-  model.node := fuzz.node
+  xbar2.node := TLAtomicAutomata() := model.node := fuzz.node
-  xbar2.node := TLAtomicAutomata()(model.node)
+  ram2.node := TLFragmenter(16, 256) := xbar2.node
-  ram2.node := TLFragmenter(16, 256)(xbar2.node)
+  xbar.node := TLWidthWidget(16) := TLHintHandler() := xbar2.node
-  xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node))
+  ram.node := TLFragmenter(4, 256) := TLBuffer() := xbar.node
-  ram.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
+  gpio.node := TLFragmenter(4, 32) := TLBuffer() := xbar.node
-  gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/HintHandler.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.min
@@ -92,12 +91,8 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
 
 object TLHintHandler
 {
-  // applied to the TL source node; y.node := TLHintHandler(x.node)
+  def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters): TLNode =
-  def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
+    LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough)).node
-    val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
-    hints.node :=? x
-    hints.node
-  }
 }
 
 /** Synthesizeable unit tests */
@@ -110,8 +105,13 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
   val model = LazyModule(new TLRAMModel("HintHandler"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
-  model.node := fuzz.node
+  (ram.node
-  ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node))))
+    := TLFragmenter(4, 256)
+    := TLDelayer(0.1)
+    := TLHintHandler()
+    := TLDelayer(0.1)
+    := model.node
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/Isolation.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.AsyncBundle
@@ -67,17 +66,3 @@ class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implici
     }
   }
 }
-
-object TLIsolation
-{
-  // applied to the TL source node; y.node := TLIsolation(fOut, fIn)(x.node)
-  // f* should insert an isolation gate between the input UInt and its result
-  // fOut is applied to data flowing from client to manager
-  // fIn  is applied to data flowing from manager to client
-  // **** WARNING: the isolation functions must bring the values to 0 ****
-  def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
-    val iso = LazyModule(new TLIsolation(fOut, fIn))
-    iso.node :=? x
-    (iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))
-  }
-}

src/main/scala/tilelink/Map.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.{min,max}
@@ -39,10 +38,5 @@ class TLMap(fn: AddressSet => BigInt)(implicit p: Parameters) extends LazyModule
 
 object TLMap
 {
-  // applied to the TL source node; y.node := TLMap(fn)(x.node)
+  def apply(fn: AddressSet => BigInt)(implicit p: Parameters): TLNode = LazyModule(new TLMap(fn)).node
-  def apply(fn: AddressSet => BigInt)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val map = LazyModule(new TLMap(fn))
-    map.node :=? x
-    map.node
-  }
 }

src/main/scala/tilelink/NodeNumberer.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 
@@ -56,10 +55,5 @@ class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Paramete
 
 object TLNodeNumberer
 {
-  // applied to the TL source node; y.node := TLBuffer(x.node)
+  def apply(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters): TLNode = LazyModule(new TLNodeNumberer(nodeAddressOffset)).node
-  def apply(nodeAddressOffset: Option[Int] = None)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val numberer = LazyModule(new TLNodeNumberer(nodeAddressOffset))
-    numberer.node :=? x
-    numberer.node
-  }
 }

src/main/scala/tilelink/RationalCrossing.scala

@@ -10,7 +10,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -79,22 +78,12 @@ class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit
 
 object TLRationalCrossingSource
 {
-  // applied to the TL source node; y.node := TLRationalCrossingSource()(x.node)
+  def apply()(implicit p: Parameters) = LazyModule(new TLRationalCrossingSource).node
-  def apply()(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLRationalOutwardNode = {
-    val source = LazyModule(new TLRationalCrossingSource)
-    source.node :=? x
-    source.node
-  }
 }
 
 object TLRationalCrossingSink
 {
-  // applied to the TL source node; y.node := TLRationalCrossingSink()(x.node)
+  def apply(direction: RationalDirection = Symmetric)(implicit p: Parameters) = LazyModule(new TLRationalCrossingSink(direction)).node
-  def apply(direction: RationalDirection = Symmetric)(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val sink = LazyModule(new TLRationalCrossingSink(direction))
-    sink.node :=? x
-    sink.node
-  }
 }
 
 @deprecated("TLRationalCrossing is fragile. Use TLRationalCrossingSource and TLRationalCrossingSink", "rocket-chip 1.2")
@@ -129,8 +118,11 @@ class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameter
   val fuzz  = LazyModule(new TLFuzzer(txns))
   val model = LazyModule(new TLRAMModel(name))
 
-  model.node := fuzz.node
+  (node
-  node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node))
+    := TLRationalCrossingSource()
+    := TLDelayer(0.25)
+    := model.node
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {
@@ -144,7 +136,11 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
   val node = TLRationalIdentityNode()
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
-  ram.node := TLFragmenter(4, 256)(TLDelayer(0.25)(TLRationalCrossingSink(direction)(node)))
+  (ram.node
+    := TLFragmenter(4, 256)
+    := TLDelayer(0.25)
+    := TLRationalCrossingSink(direction)
+    := node)
 
   lazy val module = new LazyModuleImp(this) { }
 }

src/main/scala/tilelink/RegisterRouterTest.scala

@@ -260,7 +260,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
   val fuzz = LazyModule(new TLFuzzer(txns))
   val rrtr = LazyModule(new RRTest0(0x400))
 
-  rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
+  rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished
@@ -275,7 +275,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
   val fuzz = LazyModule(new TLFuzzer(txns))
   val rrtr = LazyModule(new RRTest1(0x400))
 
-  rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
+  rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/SRAM.scala

@@ -89,8 +89,7 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
   val model = LazyModule(new TLRAMModel("SRAMSimple"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
 
-  model.node := fuzz.node
+  ram.node := TLDelayer(0.25) := model.node := fuzz.node
-  ram.node := TLDelayer(0.25)(model.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/SourceShrinker.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -75,10 +74,5 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
 
 object TLSourceShrinker
 {
-  // applied to the TL source node; y.node := TLSourceShrinker(n)(x.node)
+  def apply(maxInFlight: Int)(implicit p: Parameters): TLNode = LazyModule(new TLSourceShrinker(maxInFlight)).node
-  def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
-    shrinker.node :=? x
-    shrinker.node
-  }
 }

src/main/scala/tilelink/ToAHB.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.amba.ahb._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -187,10 +186,5 @@ class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyMo
 
 object TLToAHB
 {
-  // applied to the TL source node; y.node := TLToAHB()(x.node)
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAHB(aFlow)).node
-  def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
-    val ahb = LazyModule(new TLToAHB(aFlow))
-    ahb.node :=? x
-    ahb.node
-  }
 }

src/main/scala/tilelink/ToAPB.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.amba.apb._
@@ -86,10 +85,5 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod
 
 object TLToAPB
 {
-  // applied to the TL source node; y.node := TLToAPB()(x.node)
+  def apply(aFlow: Boolean = true)(implicit p: Parameters) = LazyModule(new TLToAPB(aFlow)).node
-  def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): APBOutwardNode = {
-    val apb = LazyModule(new TLToAPB(aFlow))
-    apb.node :=? x
-    apb.node
-  }
 }

src/main/scala/tilelink/ToAXI4.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -215,12 +214,8 @@ class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String
 
 object TLToAXI4
 {
-  // applied to the TL source node; y.node := TLToAXI4()(x.node)
+  def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(implicit p: Parameters) =
-  def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
+    LazyModule(new TLToAXI4(combinational, adapterName, stripBits)).node
-    val axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits))
-    axi4.node :=? x
-    axi4.node
-  }
 
   def sortByType(a: TLClientParameters, b: TLClientParameters): Boolean = {
     if ( a.supportsProbe && !b.supportsProbe) return false

src/main/scala/tilelink/WidthWidget.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.tilelink
 
 import Chisel._
-import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
@@ -192,12 +191,7 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
 
 object TLWidthWidget
 {
-  // applied to the TL source node; y.node := WidthWidget(x.node, 16)
+  def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = LazyModule(new TLWidthWidget(innerBeatBytes)).node
-  def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
-    val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
-    widget.node :=? x
-    widget.node
-  }
 }
 
 /** Synthesizeable unit tests */
@@ -208,12 +202,14 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
   val model = LazyModule(new TLRAMModel("WidthWidget"))
   val ram  = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
 
-  model.node := fuzz.node
+  (ram.node
-  ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)(
+    := TLDelayer(0.1)
-                if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) }
+    := TLFragmenter(4, 256)
-                else {
+    := TLWidthWidget(second)
-                  TLWidthWidget(second)(
+    := TLWidthWidget(first)
-                    TLWidthWidget(first)(TLDelayer(0.1)(model.node)))}))
+    := TLDelayer(0.1)
+    := model.node
+    := fuzz.node)
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
     io.finished := fuzz.module.io.finished

src/main/scala/tilelink/Xbar.scala

@@ -256,11 +256,10 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
   val model = LazyModule(new TLRAMModel("Xbar"))
   val xbar = LazyModule(new TLXbar)
 
-  model.node := fuzz.node
+  xbar.node := TLDelayer(0.1) := model.node := fuzz.node
-  xbar.node := TLDelayer(0.1)(model.node)
   (0 until nManagers) foreach { n =>
     val ram  = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
-    ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
+    ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
   }
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {
@@ -277,13 +276,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
 
   val fuzzers = (0 until nClients) map { n =>
     val fuzz = LazyModule(new TLFuzzer(txns))
-    xbar.node := TLDelayer(0.1)(fuzz.node)
+    xbar.node := TLDelayer(0.1) := fuzz.node
     fuzz
   }
 
   (0 until nManagers) foreach { n =>
-    val ram  = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
+    val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
-    ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
+    ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
   }
 
   lazy val module = new LazyModuleImp(this) with UnitTestModule {

src/main/scala/tilelink/package.scala

@@ -9,11 +9,5 @@ package object tilelink
 {
   type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
   type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
-  type TLNode = NodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle, TLClientPortParameters, TLManagerPortParameters, TLBundle]
+  type TLNode = SimpleNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
-  type TLAsyncInwardNode = InwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
-  type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
-  type TLRationalInwardNode = InwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
-  type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
-  type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle,
-                               TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle]
 }