riscv/rocket-chip
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merge data wmask bugfix

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This commit is contained in:
Henry Cook 2015-03-17 04:58:54 -07:00
parent dc88614094
commit 5c2461c743
2 changed files with 10 additions and 8 deletions
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11
uncore/src/main/scala/cache.scala
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@ -648,7 +648,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
amoalu.io.rhs := data_buffer.head // default amoalu.io.rhs := data_buffer.head // default
def mergeDataPut(beat: UInt, wmask: UInt, put_data: UInt) { def mergeDataPut(beat: UInt, wmask: UInt, put_data: UInt) {
data_buffer(beat) := ~wmask & data_buffer(beat) | wmask & put_data val full = FillInterleaved(8, wmask)
data_buffer(beat) := (~full & data_buffer(beat)) | (full & put_data)
wmask_buffer(beat) := wmask | wmask_buffer(beat)
} }
def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) { def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) {
@ -656,10 +658,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val new_data = data_buffer(beat) // Newly Put data is already in the buffer val new_data = data_buffer(beat) // Newly Put data is already in the buffer
amoalu.io.lhs := old_data >> xact.amo_shift_bits() amoalu.io.lhs := old_data >> xact.amo_shift_bits()
amoalu.io.rhs := new_data >> xact.amo_shift_bits() amoalu.io.rhs := new_data >> xact.amo_shift_bits()
val valid_beat = (xact.is(Acquire.putBlockType) || xact.addr_beat === beat) val valid_beat = (xact.isBuiltInType(Acquire.putBlockType) || xact.addr_beat === beat)
val wmask = Fill(dataBits, valid_beat) & wmask_buffer(beat) val wmask = Fill(dataBits, valid_beat) & FillInterleaved(8, wmask_buffer(beat))
data_buffer(beat) := ~wmask & old_data | data_buffer(beat) := ~wmask & old_data |
wmask & Mux(xact.is(Acquire.putAtomicType), wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType),
amoalu.io.out << xact.amo_shift_bits(), amoalu.io.out << xact.amo_shift_bits(),
new_data) new_data)
when(xact.is(Acquire.putAtomicType) && valid_beat) { amo_result := old_data } when(xact.is(Acquire.putAtomicType) && valid_beat) { amo_result := old_data }
@ -952,7 +954,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
val beat = io.iacq().addr_beat val beat = io.iacq().addr_beat
when(io.iacq().hasData()) { when(io.iacq().hasData()) {
mergeDataPut(beat, io.iacq().wmask(), io.iacq().data) mergeDataPut(beat, io.iacq().wmask(), io.iacq().data)
wmask_buffer(beat) := io.iacq().wmask() | wmask_buffer(beat)
//iacq_data_valid(beat) := Bool(true) //iacq_data_valid(beat) := Bool(true)
pending_writes := pending_writes | UIntToOH(io.iacq().addr_beat) pending_writes := pending_writes | UIntToOH(io.iacq().addr_beat)
} }

7
uncore/src/main/scala/tilelink.scala
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@ -106,10 +106,11 @@ class Acquire extends ClientToManagerChannel
def amo_shift_bits(dummy: Int = 0) = UInt(amoAluOperandBits)*amo_offset() def amo_shift_bits(dummy: Int = 0) = UInt(amoAluOperandBits)*amo_offset()
def wmask(dummy: Int = 0) = def wmask(dummy: Int = 0) =
Mux(isBuiltInType(Acquire.putAtomicType), Mux(isBuiltInType(Acquire.putAtomicType),
FillInterleaved(amoAluOperandBits, UIntToOH(amo_offset())), FillInterleaved(amoAluOperandBits/8, UIntToOH(amo_offset())),
Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType), Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
FillInterleaved(8, union(tlWriteMaskBits, 1)), union(tlWriteMaskBits, 1),
UInt(0, width = tlDataBits))) UInt(0, width = tlWriteMaskBits)))
def full_wmask(dummy: Int = 0) = FillInterleaved(8, wmask())
def addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte()) def addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())