riscv/rocket-chip
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merge data wmask bugfix

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Henry Cook committed 2015-03-17 13:09:47 -07:00
1 parent dc88614094
commit 5c2461c743
2 files changed
+10 -8
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uncore/src/main/scala/tilelink.scala
+4 -3
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@@ -106,10 +106,11 @@ class Acquire extends ClientToManagerChannel
def amo_shift_bits(dummy: Int = 0) = UInt(amoAluOperandBits)*amo_offset()
def wmask(dummy: Int = 0) =
Mux(isBuiltInType(Acquire.putAtomicType),
FillInterleaved(amoAluOperandBits, UIntToOH(amo_offset())),
FillInterleaved(amoAluOperandBits/8, UIntToOH(amo_offset())),
Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
FillInterleaved(8, union(tlWriteMaskBits, 1)),
UInt(0, width = tlDataBits)))
union(tlWriteMaskBits, 1),
UInt(0, width = tlWriteMaskBits)))
def full_wmask(dummy: Int = 0) = FillInterleaved(8, wmask())
def addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())