riscv/rocket-chip
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When writing full words to ITIM, ECC errors are correctable (#1148)

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* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
This commit is contained in:
Andrew Waterman
2017-12-07 16:00:26 -08:00
committed by GitHub
parent cfa819fc58
commit 5c204f98d5
2 changed files with 10 additions and 7 deletions
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2
src/main/scala/rocket/DCache.scala
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@@ -699,7 +699,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (s2_correct) { pstore1_storegen_data := s2_data_word_corrected }
// flushes
val resetting = Reg(init=Bool(true))
val resetting = Reg(init=Bool(!usingDataScratchpad))
val flushed = Reg(init=Bool(true))
val flushing = Reg(init=Bool(false))
val flushCounter = Reg(init=UInt(nSets * (nWays-1), log2Ceil(nSets * nWays)))

15
src/main/scala/rocket/ICache.scala
View File

@@ -263,6 +263,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s2_tl_error = RegEnable(s1_tl_error.asUInt.orR, s1_clk_en)
val s2_data_decoded = dECC.decode(s2_way_mux)
val s2_disparity = s2_tag_disparity || s2_data_decoded.error
val s2_full_word_write = Wire(init = false.B)
when (s2_valid && s2_disparity) { invalidate := true }
io.resp.bits.data := s2_data_decoded.uncorrected
@@ -272,20 +273,22 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr))
val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en)
val s2_report_uncorrectable_error = s2_scratchpad_hit && s2_data_decoded.uncorrectable && (s2_valid || (s2_slaveValid && !s2_full_word_write))
val s2_error_addr = scratchpadBase.map(base => Mux(s2_scratchpad_hit, base + s2_scratchpad_word_addr, 0.U)).getOrElse(0.U)
io.errors.correctable.foreach { c =>
c.valid := ((s2_valid || s2_slaveValid) && (s2_scratchpad_hit && s2_data_decoded.correctable)) || (s2_valid && !s2_scratchpad_hit && s2_disparity)
c.bits := Mux(s2_scratchpad_hit, scratchpadBase.get + s2_scratchpad_word_addr, 0.U)
c.valid := (s2_valid || s2_slaveValid) && s2_disparity && !s2_report_uncorrectable_error
c.bits := s2_error_addr
}
io.errors.uncorrectable.foreach { u =>
u.valid := (s2_valid || s2_slaveValid) && (s2_scratchpad_hit && s2_data_decoded.uncorrectable)
// the Mux is not necessary, but saves HW in BusErrorUnit because it matches c.bits above
u.bits := Mux(s2_scratchpad_hit, scratchpadBase.get + s2_scratchpad_word_addr, 0.U)
u.valid := s2_report_uncorrectable_error
u.bits := s2_error_addr
}
tl_in.map { tl =>
val respValid = RegInit(false.B)
tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid || respValid)
val s1_a = RegEnable(tl.a.bits, s0_slaveValid)
s2_full_word_write := edge_in.get.hasData(s1_a) && s1_a.mask.andR
when (s0_slaveValid) {
val a = tl.a.bits
s1s3_slaveAddr := tl.a.bits.address
@@ -324,7 +327,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
}
respValid := s2_slaveValid || (respValid && !tl.d.ready)
val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid)
val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !s2_full_word_write, s2_slaveValid)
when (s2_slaveValid) {
when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_slaveValid := true }
def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))