riscv/rocket-chip
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synced up with supervisor mode state in latest ISA simulator

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This commit is contained in:
Rimas Avizienis 2011-11-14 01:37:20 -08:00
parent 9d3471a569
commit 5b29765917
3 changed files with 10 additions and 10 deletions
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14
rocket/src/main/scala/consts.scala
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@ -146,16 +146,16 @@ object Constants
val PCR_COUNT = UFix( 4, 5); val PCR_COUNT = UFix( 4, 5);
val PCR_COMPARE = UFix( 5, 5); val PCR_COMPARE = UFix( 5, 5);
val PCR_CAUSE = UFix( 6, 5); val PCR_CAUSE = UFix( 6, 5);
val PCR_IPI = UFix( 7, 5); val PCR_PTBR = UFix( 7, 5);
val PCR_MEMSIZE = UFix( 8, 5); val PCR_SENDIPI = UFix( 8, 5);
val PCR_PTBR = UFix( 9, 5); val PCR_CLEARIPI = UFix( 9, 5);
val PCR_COREID = UFix(10, 5); val PCR_COREID = UFix(10, 5);
val PCR_NUMCORES = UFix(12, 5); val PCR_K0 = UFix(12, 5);
val PCR_K1 = UFix(13, 5);
val PCR_TOHOST = UFix(16, 5); val PCR_TOHOST = UFix(16, 5);
val PCR_FROMHOST = UFix(17, 5); val PCR_FROMHOST = UFix(17, 5);
val PCR_CONSOLE = UFix(18, 5); val PCR_CONSOLE = UFix(18, 5);
val PCR_K0 = UFix(24, 5);
val PCR_K1 = UFix(25, 5);
// definition of bits in PCR status reg // definition of bits in PCR status reg
val SR_ET = 0; // enable traps val SR_ET = 0; // enable traps
@ -185,6 +185,8 @@ object Constants
val MEMSIZE_PAGES = 0x8000; // 256 megs val MEMSIZE_PAGES = 0x8000; // 256 megs
val MEMSIZE_BYTES = MEMSIZE_PAGES*8192; val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
val START_ADDR = 0x2000;
val HAVE_FPU = Bool(false); val HAVE_FPU = Bool(false);
val HAVE_VEC = Bool(false); val HAVE_VEC = Bool(false);
} }

2
rocket/src/main/scala/dpath.scala
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@ -158,7 +158,7 @@ class rocketDpath extends Component
UFix(0, VADDR_BITS))))))))))); UFix(0, VADDR_BITS)))))))))));
when (!io.host.start){ when (!io.host.start){
if_reg_pc <== UFix(0, VADDR_BITS); //32'hFFFF_FFFC; if_reg_pc <== UFix(START_ADDR, VADDR_BITS);
} }
when (!io.ctrl.stallf) { when (!io.ctrl.stallf) {
if_reg_pc <== if_next_pc; if_reg_pc <== if_next_pc;

2
rocket/src/main/scala/dpath_util.scala
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@ -166,9 +166,7 @@ class rocketDpathPCR extends Component
is (PCR_COUNT) { rdata <== Cat(Fill(32, reg_count(31)), reg_count); } is (PCR_COUNT) { rdata <== Cat(Fill(32, reg_count(31)), reg_count); }
is (PCR_COMPARE) { rdata <== Cat(Fill(32, reg_compare(31)), reg_compare); } is (PCR_COMPARE) { rdata <== Cat(Fill(32, reg_compare(31)), reg_compare); }
is (PCR_CAUSE) { rdata <== Cat(Bits(0,59), reg_cause); } is (PCR_CAUSE) { rdata <== Cat(Bits(0,59), reg_cause); }
is (PCR_MEMSIZE) { rdata <== Bits(MEMSIZE_PAGES,64); }
is (PCR_COREID) { rdata <== Bits(COREID,64); } is (PCR_COREID) { rdata <== Bits(COREID,64); }
is (PCR_NUMCORES) { rdata <== Bits(NUMCORES,64); }
is (PCR_FROMHOST) { rdata <== Cat(Fill(32, reg_fromhost(31)), reg_fromhost); } is (PCR_FROMHOST) { rdata <== Cat(Fill(32, reg_fromhost(31)), reg_fromhost); }
is (PCR_TOHOST) { rdata <== Cat(Fill(32, reg_tohost(31)), reg_tohost); } is (PCR_TOHOST) { rdata <== Cat(Fill(32, reg_tohost(31)), reg_tohost); }
is (PCR_K0) { rdata <== reg_k0; } is (PCR_K0) { rdata <== reg_k0; }